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ATmega325P датащи(PDF) 163 Page - ATMEL Corporation |
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ATmega325P датащи(HTML) 163 Page - ATMEL Corporation |
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163 / 364 page ![]() 163 8023F–AVR–07/09 ATmega325P/3250P 18. USART0 18.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous Communication Mode 18.2 Overview The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. A simplified block diagram of the USART Transmitter is shown in Figure 18-1 on page 164. CPU accessible I/O Registers and I/O pins are shown in bold. The Power Reduction USART bit, PRUSART0, in ”PRR – Power Reduction Register” on page 44 must be written to zero to enable USART0 module. |
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