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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATmega325P датащи(PDF) 133 Page - ATMEL Corporation |
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ATmega325P датащи(HTML) 133 Page - ATMEL Corporation |
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133 / 364 page  133 8023F–AVR–07/09 ATmega325P/3250P 15.11.7 ICR1H and ICR1L – Input Capture Register 1 The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See Section “15.3” on page 110. 15.11.8 TIMSK1 – Timer/Counter1 Interrupt Mask Register • Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (See Section “11.” on page 53.) is executed when the ICF1 Flag, located in TIFR1, is set. • Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (See Section “11.” on page 53.) is executed when the OCF1B Flag, located in TIFR1, is set. • Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (See Section “11.” on page 53.) is executed when the OCF1A Flag, located in TIFR1, is set. • Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector (See Section “11.” on page 53.) is executed when the TOV1 Flag, located in TIFR1, is set. 15.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register Bit 7 65 43 21 0 (0x87) ICR1[15:8] ICR1H (0x86) ICR1[7:0] ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 543 2 1 0 (0x6F) – –ICIE1 – – OCIE1B OCIE1A TOIE1 TIMSK1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 543210 0x16 (0x36) – –ICF1 – – OCF1B OCF1A TOV1 TIFR1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 000000 |
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