ATmega169P datasheet(390/393 Pages) ATMEL

390 / 393 page

8018M–AVR–07/09

ATmega169P

22.6Changing Channel or Reference Selection .........................................................220

22.7ADC Noise Canceler ...........................................................................................221

22.8ADC Conversion Result .......................................................................................226

22.9ADC Register Description ....................................................................................228

LCD Controller ...................................................................................... 233

23.1Features ..............................................................................................................233

23.2Overview ..............................................................................................................233

23.3Mode of Operation ...............................................................................................236

23.4LCD Usage ..........................................................................................................241

23.5LCD Register Description ....................................................................................245

JTAG Interface and On-chip Debug System ...................................... 251

24.1Overview ..............................................................................................................251

24.2TAP – Test Access Port ......................................................................................252

24.3TAP Controller .....................................................................................................254

24.4Using the Boundary-scan Chain ..........................................................................255

24.5Using the On-chip Debug System .......................................................................255

24.6On-chip Debug Specific JTAG Instructions .........................................................256

24.7On-chip Debug Related Register in I/O Memory .................................................257

24.8Using the JTAG Programming Capabilities .........................................................257

24.9Bibliography .........................................................................................................257

IEEE 1149.1 (JTAG) Boundary-scan ................................................... 258

25.1Features ..............................................................................................................258

25.2System Overview .................................................................................................258

25.3Data Registers .....................................................................................................259

25.4Boundary-scan Specific JTAG Instructions .........................................................260

25.5Boundary-scan Chain ..........................................................................................261

25.6Boundary-scan Order ..........................................................................................271

25.7Boundary-scan Description Language Files ........................................................277

25.8Boundary-scan Related Register in I/O Memory .................................................278

Boot Loader Support – Read-While-Write Self-Programming ......... 279

26.1Features ..............................................................................................................279

26.2Overview ..............................................................................................................279

26.3Application and Boot Loader Flash Sections .......................................................279

26.4Read-While-Write and No Read-While-Write Flash Sections ..............................280

26.5Boot Loader Lock Bits .........................................................................................283

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