ATmega169P datasheet(323/393 Pages) ATMEL

323 / 393 page

323

8018N–AVR–08/09

ATmega169P

ture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is

post-incremented after reading each high byte, including the first read byte. This ensures that

the first data is captured from the first address set up by PROG_COMMANDS, and reading the

last location in the page makes the program counter increment into the next page.

Figure 27-17. Flash Data Byte Register

The state machine controlling the Flash Data Byte Register is clocked by TCK. During normal

operation in which eight bits are shifted for each Flash byte, the clock cycles needed to navigate

through the TAP controller automatically feeds the state machine for the Flash Data Byte Regis-

ter with sufficient number of clock pulses to complete its operation transparently for the user.

However, if too few bits are shifted between each Update-DR state during page load, the TAP

controller should stay in the Run-Test/Idle state for some TCK cycles to ensure that there are at

least 11 TCK cycles between each Update-DR state.

27.9.12

Programming Algorithm

All references below of type “1a”, “1b”, and so on, refer to Table 27-17 on page 319.

27.9.13

Entering Programming Mode

Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register.

Enter instruction PROG_ENABLE and shift 0b1010_0011_0111_0000 in the Program-

ming Enable Register.

27.9.14

Leaving Programming Mode

Enter JTAG instruction PROG_COMMANDS.

Disable all programming instructions by using no operation instruction 11a.

Enter instruction PROG_ENABLE and shift 0b0000_0000_0000_0000 in the program-

ming Enable Register.

Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register.

TDI

TDO

Flash

EEPROM

Fuses

Lock Bits

STROBES

ADDRESS

State

Machine

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