ATmega169P datasheet(235/393 Pages) ATMEL

235 / 393 page

235

8018N–AVR–08/09

ATmega169P

To energize a segment, an absolute voltage above a certain threshold must be applied. This is

done by letting the output voltage on corresponding COM pin and SEG pin have opposite phase.

For display with more than one common, one (1/2 bias) or two (1/3 bias) additional voltage lev-

els must be applied. Otherwise, non-energized segments on COM0 would be energized for all

non-selected common.

Addressing COM0 starts a frame by driving opposite phase with large amplitude out on COM0

compared to none addressed COM lines. Non-energized segments are in phase with the

addressed COM0, and energized segments have opposite phase and large amplitude. For

waveform figures refer to ”Mode of Operation” on page 236. Latched data from LCDDR4 -

LCDDR0 is multiplexed into the decoder. The decoder is controlled from the LCD timing and

sets up signals controlling the analog switches to produce an output waveform. Next, COM1 is

addressed, and latched data from LCDDR9 - LCDDR5 is input to decoder. Addressing continu-

ous until all COM lines are addressed according to number of common (duty). The display data

are latched before a new frame start.

23.2.5

LCD Contrast Controller/Power Supply

The peak value (V

LCD) on the output waveform determines the LCD Contrast. VLCD is controlled

by software from 2.6V to 3.35V independent of V

CC. An internal signal inhibits output to the LCD

until V

LCD has reached its target value.

23.2.6

LCDCAP

An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as shown in Fig-

ure 23-2. This capacitor acts as a reservoir for LCD power (V

LCD). A large capacitance reduces

ripple on V

LCD but increases the time until VLCD reaches its target value.

It is possible to use an external power supply. This power can be applied to LCDCAP before

CC. Externally applied VLCD can be both above and below VCC. Maximum VLCD is 5.5V

Figure 23-2. LCDCAP Connection

23.2.7

LCD Buffer Driver

Intermediate voltage levels are generated from buffers/drivers. The buffers are active the

amount of time specified by LCDDC[2:0] in ”LCDCCR – LCD Contrast Control Register” on page

249. Then LCD output pins are tri-stated and buffers are switched off. Shortening the drive time

will reduce power consumption, but displays with high internal resistance or capacitance may

need longer drive time to achieve sufficient contrast.

LCDCAP

LCD

(Optional)

ATmega169P датащи(PDF) 235 Page - ATMEL Corporation

ATmega169P датащи(HTML) 235 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL