ATmega169P datasheet(199/393 Pages) ATMEL

199 / 393 page

199

8018N–AVR–08/09

ATmega169P

20. USI – Universal Serial Interface

The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial

communication. Combined with a minimum of control software, the USI allows significantly

higher transfer rates and uses less code space than solutions based on software only. Interrupts

are included to minimize the processor load. The main features of the USI are:

• Two-wire Synchronous Data Transfer (Master or Slave)

• Three-wire Synchronous Data Transfer (Master or Slave)

• Data Received Interrupt

• Wakeup from Idle Mode

• In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode

• Two-wire Start Condition Detector with Interrupt Capability

20.1

Overview

A simplified block diagram of the USI is shown on Figure 20-1. For the actual placement of I/O

pins, refer to ”64A (TQFP)and 64M1 (QFN/MLF) Pinout ATmega169P” on page 2. CPU accessi-

ble I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O

Figure 20-1. Universal Serial Interface, Block Diagram

The 8-bit Shift Register is directly accessible via the data bus and contains the incoming and

outgoing data. The register has no buffering so the data must be read as quickly as possible to

ensure that no data is lost. The most significant bit is connected to one of two output pins

depending of the wire mode configuration. A transparent latch is inserted between the Serial

edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin

independent of the configuration.

The 4-bit counter can be both read and written via the data bus, and can generate an overflow

interrupt. Both the Serial Register and the counter are clocked simultaneously by the same clock

source. This allows the counter to count the number of bits received or transmitted and generate

Two-wire Clock

Control Unit

(Output only)

DI/SDA

(Input/Open Drain)

USCK/SCL

(Input/Open Drain)

4-bit Counter

USIDR

USISR

USICR

CLOCK

HOLD

TIM0 COMP

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