ATtiny87-15XZ datasheet(40/282 Pages) ATMEL

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7728D–AVR–07/09

ATtiny87/ATtiny167

start-up time, the clock frequency and, of course, if the clock is alive. The user’s code has to

differentiate between ‘no_clock_signal’ and ‘clock_signal_not_yet_available’ condition.

• Bits 3:0 – CLKC3:0: Clock Control Bits 3 - 0

These bits define the command to provide to the ‘Clock Switch’ module. The special write pro-

cedure must be followed to change the CLKC3..0 bits (See ”Bit 7 – CLKCCE: Clock Control

Change Enable” on page 39.).

Write the Clock Control Change Enable (CLKCCE) bit to one and all other bits in

CLKCSR to zero.

Within 4 cycles, write the desired value to CLKCSR register while clearing CLKCCE

bit.

Interrupts should be disabled when setting CLKCSR register in order not to disturb the

procedure.

4.5.4

CLKSELR - Clock Selection Register

• Bit 7– Res: Reserved Bit

This bit is reserved bit in the ATtiny87/167 and will always read as zero.

• Bit 6 – COUT: Clock Out

The COUT bit is initialized with ~(CKOUT) Fuse bit.

The COUT bit is only used in case of ‘CKOUT’ command. Refer to Section 4.2.7 “Clock Output

Buffer” on page 31 for using.

In case of ‘Recover System Clock Source’ command, COUT it is not affected (no recovering of

this setting).

Table 4-11.

Clock command list.

Clock Command

CLKC3..0

No command

0000 b

Disable clock source

0001

Enable clock source

0010

Request for clock

availability

0011 b

Clock source switch

0100

Recover system clock source code

0101

Enable watchdog in automatic reload mode

0110 b

CKOUT command

0111

No command

1xxx b

Bit

543

210

COUT

CSUT1

CSUT0

CSEL3

CSEL2

CSEL1

CSEL0

CLKSELR

Read/Write

R/W

Initial Value

~ (CKOUT)

fuse

SUT1..0

fuses

CKSEL3..0

fuses

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