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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATtiny87-15XZ датащи(PDF) 39 Page - ATMEL Corporation |
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ATtiny87-15XZ датащи(HTML) 39 Page - ATMEL Corporation |
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39 / 282 page  39 7728D–AVR–07/09 ATtiny87/ATtiny167 4.5.3 CLKCSR – Clock Control & Status Register • Bit 7 – CLKCCE: Clock Control Change Enable The CLKCCE bit must be written to logic one to enable change of the CLKCSR bits. The CLKCCE bit is only updated when the other bits in CLKCSR are simultaneously written to zero. CLKCCE is cleared by hardware four cycles after it is written or when the CLKCSR bits are written. Rewriting the CLKCCE bit within this time-out period does neither extend the time-out period, nor clear the CLKCCE bit. • Bits 6:5 – Res: Reserved Bits These bits are reserved bits in the ATtiny87/167 and will always read as zero. • Bits 4 – CLKRDY: Clock Ready Flag This flag is the output of the ‘Clock Availability ’ logic. This flag is cleared by the ‘Request for Clock Availability’ command or ‘Enable Clock Source’ command being entered. It is set when ‘Clock Availability’ logic confirms that the (selected) clock is running and is sta- ble. The delay from the request and the flag setting is not fixed, it depends on the clock Table 4-10. Clock Prescaler Select CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor 000 0 1 000 1 2 001 0 4 001 1 8 010 0 16 010 1 32 011 0 64 011 1 128 100 0 256 1 0 0 1 Reserved 1 0 1 0 Reserved 1 0 1 1 Reserved 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved Bit 7 65 4 3210 CLKCCE – – CLKRDY CLKC3 CLKC2 CLKC1 CLKC0 CLKCSR Read/Write R/W R R R R/W R/W R/W R/W Initial Value 0 00 0 0000 |
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