AT91SAM9G20 datasheet(28/832 Pages) ATMEL

28 / 832 page

6384D–ATARM–04-May-09

AT91SAM9G20 Preliminary

– Source 0 is reserved for the Fast Interrupt Input (FIQ)

– Source 1 is reserved for system peripherals

– Programmable Edge-triggered or Level-sensitive Internal Sources

– Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive

• Three External Sources plus the Fast Interrupt signal

• 8-level Priority Controller

– Drives the Normal Interrupt of the processor

– Handles priority of the interrupt sources 1 to 31

– Higher priority interrupts can be served during service of lower priority interrupt

• Vectoring

– Optimizes Interrupt Service Routine Branch and Execution

– One 32-bit Vector Register per interrupt source

– Interrupt Vector Register reads the corresponding current Interrupt Vector

•Protect Mode

– Easy debugging by preventing automatic operations when protect models are

enabled

•Fast Forcing

– Permits redirecting any normal interrupt source on the Fast Interrupt of the

processor

9.11

Debug Unit

• Composed of two functions:

–Two-pin UART

– Debug Communication Channel (DCC) support

•Two-pin UART

– Implemented features are 100% compatible with the standard Atmel

® USART

– Independent receiver and transmitter with a common programmable Baud Rate

Generator

– Even, Odd, Mark or Space Parity Generation

– Parity, Framing and Overrun Error Detection

– Automatic Echo, Local Loopback and Remote Loopback Channel Modes

– Support for two PDC channels with connection to receiver and transmitter

• Debug Communication Channel Support

– Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from

the ARM Processor’s ICE Interface

9.12

Chip Identification

• Chip ID:0x019905A1

• JTAG ID: 0x05B2403F

• ARM926 TAP ID:0x0792603F

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