AT91SAM9G20 datasheet(21/832 Pages) ATMEL

21 / 832 page

6384D–ATARM–04-May-09

AT91SAM9G20 Preliminary

When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an

external memory. This is done via hardware at reset.

Note:

Memory blocks not affected by these parameters can always be seen at their specified base

addresses. See the complete memory map presented in Figure 8-1 on page 19.

The AT91SAM9G20 matrix manages a boot memory that depends on the level on the BMS pin

at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved

for this purpose.

If BMS is detected at 1, the boot memory is the embedded ROM.

If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the

External Bus Interface.

8.1.1.1

BMS = 1, Boot on Embedded ROM

The system boots using the Boot Program.

• Boot on slow clock (On-chip RC or 32,768 Hz)

• Auto baudrate detection

• Downloads and runs an application from external storage media into internal SRAM

• Downloaded code size depends on embedded SRAM size

• Automatic detection of valid application

• Bootloader on a non-volatile memory

– SDCard (boot ROM does not support high capacity SDCards.)

–NAND Flash

– SPI DataFlash® and Serial Flash connected on NPCS0 and NPCS1 of the SPI0

– EEPROM on TWI

• SAM-BA

® Boot in case no valid program is detected in external NVM, supporting

– Serial communication on a DBGU

– USB Device HS Port

8.1.1.2

BMS = 0, Boot on External Memory

• Boot on slow clock (On-chip RC or 32,768 Hz)

• Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit

data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory.

The customer-programmed software must perform a complete configuration.

To speed up the boot sequence when booting at 32 kHz EBI CS0 (BMS=0), the user must take

the following steps:

Program the PMC (main oscillator enable or bypass mode).

Program and start the PLL.

Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them

to the new clock.

Switch the main clock to the new value.

8.2

External Memories

The external memories are accessed through the External Bus Interface. Each Chip Select line

has a 256-Mbyte memory area assigned.

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