ATmega165 datasheet(181/336 Pages) ATMEL

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181

ATmega165/V

2573G–AVR–07/09

Start Condition Detector

The start condition detector is shown in Figure 81. The SDA line is delayed (in the range

of 50 to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is

only enabled in Two-wire mode.

The start condition detector is working asynchronously and can therefore wake up the

processor from the Power-down sleep mode. However, the protocol used might have

restrictions on the SCL hold time. Therefore, when using this feature in this case the

Oscillator start-up time set by the CKSEL Fuses (see “Clock Systems and their Distribu-

tion” on page 23) must also be taken into the consideration. Refer to the USISIF bit

description on page 182 for further details.

Clock speed considerations.

Maximum frequency for SCL and SCK is f

CK /4. This is also the maximum data transmit

and receieve rate in both two- and three-wire mode. In two-wire slave mode the Two-

wire Clock Control Unit will hold the SCL low until the slave is ready to receive more

data. This may reduce the actual data rate in two-wire mode.

Alternative USI Usage

When the USI unit is not used for serial communication, it can be set up to do alternative

tasks due to its flexible design.

Half-duplex Asynchronous

Data Transfer

By utilizing the Shift Register in Three-wire mode, it is possible to implement a more

compact and higher performance UART than by software only.

4-bit Counter

The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note

that if the counter is clocked externally, both clock edges will generate an increment.

12-bit Timer/Counter

Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit

counter.

Edge Triggered External

Interrupt

By setting the counter to maximum value (F) it can function as an additional external

interrupt. The Overflow Flag and Interrupt Enable bit are then used for the external inter-

rupt. This feature is selected by the USICS1 bit.

Software Interrupt

The counter overflow interrupt can be used as a software interrupt triggered by a clock

strobe.

USI Register

Descriptions

USI Data Register – USIDR

The USI uses no buffering of the Serial Register, i.e., when accessing the Data Register

(USIDR) the Serial Register is accessed directly. If a serial clock occurs at the same

cycle the register is written, the register will contain the value written and no shift is per-

formed. A (left) shift operation is performed depending of the USICS1..0 bits setting. The

shift operation can be controlled by an external clock edge, by a Timer/Counter0 Com-

pare Match, or directly by software using the USICLK strobe bit. Note that even when no

wire mode is selected (USIWM1..0 = 0) both the external data input (DI/SDA) and the

external clock input (USCK/SCL) can still be used by the Shift Register.

The output pin in use, DO or SDA depending on the wire mode, is connected via the out-

put latch to the most significant bit (bit 7) of the Data Register. The output latch is open

Bit

MSB

LSB

USIDR

Read/Write

R/W

Initial Value

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