ATmega165 datasheet(177/336 Pages) ATMEL

177 / 336 page

177

ATmega165/V

2573G–AVR–07/09

The Three-wire mode timing is shown in Figure 78. At the top of the figure is a USCK

cycle reference. One bit is shifted into the USI Shift Register (USIDR) for each of these

cycles. The USCK timing is shown for both external clock modes. In External Clock

mode 0 (USICS0 = 0), DI is sampled at positive edges, and DO is changed (Data Regis-

ter is shifted by one) at negative edges. External Clock mode 1 (USICS0 = 1) uses the

opposite edges versus mode 0, i.e., samples data at negative and changes the output at

positive edges. The USI clock modes corresponds to the SPI data mode 0 and 1.

Referring to the timing diagram (Figure 78.), a bus transfer involves the following steps:

The Slave device and Master device sets up its data output and, depending on

the protocol used, enables its output driver (mark A and B). The output is set up

by writing the data to be transmitted to the Serial Data Register. Enabling of the

output is done by setting the corresponding bit in the port Data Direction Regis-

ter. Note that point A and B does not have any specific order, but both must be at

least one half USCK cycle before point C where the data is sampled. This must

be done to ensure that the data setup requirement is satisfied. The 4-bit counter

is reset to zero.

The Master generates a clock pulse by software toggling the USCK line twice (C

and D). The bit value on the slave and master’s data input (DI) pin is sampled by

the USI on the first edge (C), and the data output is changed on the opposite

edge (D). The 4-bit counter will count both edges.

Step 2. is repeated eight times for a complete register (byte) transfer.

After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indi-

cate that the transfer is completed. The data bytes transferred must now be

processed before a new transfer can be initiated. The overflow interrupt will wake

up the processor if it is set to Idle mode. Depending of the protocol used the

slave device can now set its output to high impedance.

SPI Master Operation

Example

The following code demonstrates how to use the USI module as a SPI Master:

SPITransfer:

sts

USIDR,r16

ldi

r16,(1<<USIOIF)

sts

USISR,r16

ldi

r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC)

SPITransfer_loop:

sts

USICR,r16

lds

r16, USISR

sbrs

r16, USIOIF

rjmp

SPITransfer_loop

lds

r16,USIDR

ret

The code is size optimized using only eight instructions (+ ret). The code example

assumes that the DO and USCK pins are enabled as output in the DDRE Register. The

value stored in register r16 prior to the function is called is transferred to the Slave

device, and when the transfer is completed the data received from the Slave is stored

back into the r16 Register.

The second and third instructions clears the USI Counter Overflow Flag and the USI

counter value. The fourth and fifth instruction set Three-wire mode, positive edge Shift

ATmega165 датащи(PDF) 177 Page - ATMEL Corporation

ATmega165 датащи(HTML) 177 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL