ATmega128 datasheet(108/386 Pages) ATMEL

108 / 386 page

108

2467S–AVR–07/09

ATmega128

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When writing to one of the registers TCNT0, OCR0, or TCCR0, the value is transferred to a

temporary register, and latched after two positive edges on TOSC1. The user should not

write a new value before the contents of the Temporary Register have been transferred to its

destination. Each of the three mentioned registers have their individual temporary register,

which means that e.g., writing to TCNT0 does not disturb an OCR0 write in progress. To

detect that a transfer to the destination register has taken place, the Asynchronous Status

•

When entering Power-save or Extended Standby mode after having written to TCNT0,

OCR0, or TCCR0, the user must wait until the written register has been updated if

Timer/Counter0 is used to wake up the device. Otherwise, the MCU will enter sleep mode

before the changes are effective. This is particularly important if the Output Compare0

interrupt is used to wake up the device, since the output compare function is disabled during

writing to OCR0 or TCNT0. If the write cycle is not finished, and the MCU enters sleep mode

before the OCR0UB bit returns to zero, the device will never receive a compare match

interrupt, and the MCU will not wake up.

•

If Timer/Counter0 is used to wake the device up from Power-save or Extended Standby

mode, precautions must be taken if the user wants to re-enter one of these modes: The

interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and re-

entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the

device will fail to wake up. If the user is in doubt whether the time before re-entering Power-

save or Extended Standby mode is sufficient, the following algorithm can be used to ensure

that one TOSC1 cycle has elapsed:

Write a value to TCCR0, TCNT0, or OCR0.

Wait until the corresponding Update Busy flag in ASSR returns to zero.

Enter Power-save or Extended Standby mode.

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When the asynchronous operation is selected, the 32.768 kHZ Oscillator for Timer/Counter0

is always running, except in Power-down and Standby modes. After a Power-up Reset or

wake-up from Power-down or Standby mode, the user should be aware of the fact that this

Oscillator might take as long as one second to stabilize. The user is advised to wait for at

least one second before using Timer/Counter0 after power-up or wake-up from Power-down

or Standby mode. The contents of all Timer/Counter0 Registers must be considered lost

after a wake-up from Power-down or Standby mode due to unstable clock signal upon start-

up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin.

•

Description of wake up from Power-save or Extended Standby mode when the timer is

clocked asynchronously: When the interrupt condition is met, the wake up process is started

on the following cycle of the timer clock, that is, the timer is always advanced by at least one

before the processor can read the counter value. After wake-up, the MCU is halted for four

cycles, it executes the interrupt routine, and resumes execution from the instruction

following SLEEP.

•

Reading of the TCNT0 Register shortly after wake-up from Power-save may give an

incorrect result. Since TCNT0 is clocked on the asynchronous TOSC clock, reading TCNT0

must be done through a register synchronized to the internal I/O clock domain.

Synchronization takes place for every rising TOSC1 edge. When waking up from Power-

save mode, and the I/O clock (clk

I/O) again becomes active, TCNT0 will read as the previous

value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC

clock after waking up from Power-save mode is essentially unpredictable, as it depends on

the wake-up time. The recommended procedure for reading TCNT0 is thus as follows:

Write any value to either of the registers OCR0 or TCCR0.

Wait for the corresponding Update Busy Flag to be cleared.

Read TCNT0.

ATmega128 датащи(PDF) 108 Page - ATMEL Corporation

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