ATmega128 datasheet(109/386 Pages) ATMEL

109 / 386 page

109

2467S–AVR–07/09

ATmega128

•

During asynchronous operation, the synchronization of the interrupt flags for the

asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore

advanced by at least one before the processor can read the timer value causing the setting

of the interrupt flag. The output compare pin is changed on the timer clock and is not

synchronized to the processor clock.

Timer/Counter

Interrupt Mask

• Bit 1 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable

When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the

Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if

a compare match in Timer/Counter0 occurs, i.e., when the OCF0 bit is set in the Timer/Counter

Interrupt Flag Register – TIFR.

• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an

overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt

Flag Register – TIFR.

Timer/Counter

Interrupt Flag Register

– TIFR

• Bit 1 – OCF0: Output Compare Flag 0

The OCF0 bit is set (one) when a compare match occurs between the Timer/Counter0 and the

data in OCR0 – Output Compare Register0. OCF0 is cleared by hardware when executing the

corresponding interrupt handling vector. Alternatively, OCF0 is cleared by writing a logic one to

the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Compare Match Interrupt Enable), and

OCF0 are set (one), the Timer/Counter0 Compare Match Interrupt is executed.

• Bit 0 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hard-

ware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared

by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Inter-

rupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow Interrupt is executed. In

PWM mode, this bit is set when Timer/Counter0 changes counting direction at $00.

Bit

765

210

OCIE2

TOIE2

TICIE1

OCIE1A

OCIE1B

TOIE1

OCIE0

TOIE0

TIMSK

Read/Write

R/W

Initial Value

Bit

765

4321

OCF2

TOV2

ICF1

OCF1A

OCF1B

TOV1

OCF0

TOV0

TIFR

Read/Write

R/W

Initial Value

000

0000

ATmega128 датащи(PDF) 109 Page - ATMEL Corporation

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