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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATmega128 датащи(PDF) 104 Page - ATMEL Corporation |
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ATmega128 датащи(HTML) 104 Page - ATMEL Corporation |
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104 / 386 page  104 2467S–AVR–07/09 ATmega128 Figure 44. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Pres- caler (f clk_I/O/8) 8-bit Timer/Counter Register Description Timer/Counter Control Register – TCCR0 • Bit 7 – FOC0: Force Output Compare The FOC0 bit is only active when the WGM bits specify a non-PWM mode. However, for ensur- ing compatibility with future devices, this bit must be set to zero when TCCR0 is written when operating in PWM mode. When writing a logical one to the FOC0 bit, an immediate compare match is forced on the waveform generation unit. The OC0 output is changed according to its COM01:0 bits setting. Note that the FOC0 bit is implemented as a strobe. Therefore it is the value present in the COM01:0 bits that determines the effect of the forced compare. A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0 as TOP. The FOC0 bit is always read as zero. • Bit 6, 3 – WGM01:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 52 and “Modes of Operation” on page 98. OCFn OCRn TCNTn (CTC) TOP TOP - 1 TOP BOTTOM BOTTOM + 1 clk I/O clk Tn (clk I/O/8) Bit 7 6 5 4 3 210 FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 TCCR0 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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