EM68932DVKB datasheet(9/40 Pages) ETRON

9 / 40 page

EtronTech

EM68932DVKB

Etron Confidential

Rev. 1.0

Aug. 2009

Extended Mode Register Set (EMRS )

The Extended Mode Register is designed to support Partial Array Self Refresh and Driver Strength. The

EMRS cycle is not mandatory, and the EMRS command needs to be issued only when either PASR or DS

is used. The Extended Mode Register is written by asserting Low on CS , RAS , CAS , WE , and BA0 and

High on BA1 (the device should have all banks idle with no bursts in progress prior to writing into the

Extended Mode Register, and CKE should be High). Values stored in the register will be retained until the

device. The state of address pins A0~A11 and BA0, BA1 in the same cycle in which CS , RAS , CAS

and WE are asserted Low is written into the Extended Mode Register. Two clock cycles, tMRD, are required

to complete the write operation in the Extended Mode Register. A0~A2 are used for Partial Array Self

Refresh and A5~A6 are used for Driver Strength. An automatic Temperature Compensated Self Refresh

function is included with a temperature sensor embedded into this device. A3~A4 are no longer used to

control this function; any inputs applied to A3~A4 during EMRS are ignored. All the other address pins,

A7~A11 and BA0, must be set to Low for proper EMRS operation. Refer to the tables below for specific

codes. If the user does not write values to the Extended Mode Register, DS defaults to Full Strength; and

PASR defaults to the Full Array.

Table 6. Extend Mode Register Bitmap

BA1 BA0 A11 A10 A9

Address Field

PASR

Extended Mode Register

Drive Strength

A2 A1 A0 Partial Array Self Refresh Coverage

Full Strength

Full Array (All Banks)

1/2 Strength

Half of Full Array (BA1=0)

1/4 Strength

Quarter of Full Array (BA1=BA0=0)

1/8 Strength

Reserved

100

Reserved

101

Reserved

110

Reserved

111

Reserved

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