ICS8735-21

700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR

IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR

18

ICS8735AM-21 REV. A JULY 31, 2008

Package Outline - K Suffix for 32 Lead VFQFN

The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not

intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package

dimensions are in Table 9B below.

Table 9B. Package Dimensions for 32 Lead VFQFN

Reference Document: JEDEC Publication 95, MO-220

JEDEC Variation: VHHD-2/-4

All Dimensions in Millimeters

Symbol

Minimum

Nominal

Maximum

N

32

A

0.80

1.00

A1

00.05

A3

0.25 Ref.

b

0.18

0.25

0.30

8

D & E

5.00 Basic

D2 & E2

3.0

3.3

e

0.50 Basic

L

0.30

0.40

0.50

To p View

Ind exArea

D

Chamfer 4x

0.6 x 0.6 max

OPTIONAL

Anvil

Singula tion

A

0. 08

C

C

A3

A1

S eating Plan e

E2

E2

2

L

(N

-1)x e

(R ef.)

(Ref.)

N & N

Even

N

e

D2

2

D2

(Ref.)

N & N

Odd

1

2

e

2

(Ty p.)

If N & N

are Even

(N -1)x e

(Re f.)

b

Th er mal

Ba se

N

OR