ADP1043A datasheet(21/72 Pages) AD

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ADP1043A

Rev. 0 | Page 21 of 72

Figure 25 shows the possible signals on the share bus.

LOGIC 1

LOGIC 0

IDLE

BIT

tBIT

Figure 25. Share Bus High, Low, and Idle Bits

The length of a bit (tBIT) is fixed at 10 μs. A Logic 1 is defined as

a high-to-low transition at the start of the bit and a low-to-high

transition at 75% of tBIT. A Logic 0 is defined as a high-to-low

transition at the start of the bit and a low-to-high transition at

25% of tBIT.

The bus is idle when it is high during the whole period of tBIT.

All other activity on the bus is illegal. Glitches up to tGLITCH

(200 ns) are ignored.

The digital word that represents the current information is eight

bits long. The ADP1043A takes the eight MSBs of the CS1 or CS2

reading (whichever the user chooses as the current share signal)

and uses this reading as the digital word. When read, the share

bus value at any given time is equal to the CS1 or CS2 current

reading (see Figure 26).

Digital Share Bus Scheme

Each power supply compares the digital word that it is outputting

with the digital words of all the other supplies on the bus.

Round 1

In Round 1, every supply first places its MSB on the bus. If a

supply senses that its MSB is the same as the value on the bus, it

continues to Round 2. If a supply senses that its MSB is less than

the value on the bus, it means that this supply must be a slave.

When a supply becomes a slave, it stops communicating on the

share bus because it knows that it is not the master. The supply

then increases its output voltage in an attempt to share more

current.

If two units have the same MSB, they both continue to Round 2,

because either of them could be the master.

Round 2

In Round 2, all supplies that are still communicating on the bus

place their second MSB on the share bus. If a supply senses that

its MSB is less than the value on the bus, it means that this

supply must be a slave and it stops communicating.

Round 3 to Round 8

The same algorithm is repeated for up to eight rounds to allow

supplies to compare their digital words and, in this way, to

determine whether each unit is the master or a slave.

Digital Share Bus Configuration

The digital share bus can be configured in various ways.

The bandwidth of the share bus loop is programmable in

the current of the master can be selected by programming

can be used as the current share signal by programming

A load line may be required between PSUs when using a digital

share bus. A minimum impedance of 15 mΩ is recommended

between the remote voltage sense node and the load.

CURRENT

SENSE

ADC

15.26µV = 1 LSB

35mV/15.26µV = 2293

MASTER

35mV

–

DIGITAL

WORD

DIGITAL

FILTER

÷16

12-BIT

2293 DEC

0x8F5

8-BIT

143 DEC

0x8F

SHAREi

CS2+

CS2–

VDD

BUS

8-BIT

WORD

0x8F

8-BIT

WORD

0x8F

SHAREo

IOUT = 35A

Ω

PSU A

Figure 26. How the Share Bus Generates the Digital Word to Place on the Digital Share Bus

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