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ADP1043A датащи(PDF) 50 Page - Analog Devices |
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ADP1043A датащи(HTML) 50 Page - Analog Devices |
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50 / 72 page ![]() ADP1043A Rev. 0 | Page 50 of 72 PWM AND SYNCHRONOUS RECTIFIER TIMING REGISTERS Figure 36 and Table 58 to Table 88 describe the implementation and programming of the seven PWM signals that are output from the ADP1043A. In general, it is recommended that t1 be set to 0 and that t1 be set as the reference point for the other signals. tPERIOD tPERIOD t14 t11 t13 t12 t9 t10 t7 t8 t6 t1 t5 t3 t4 t2 PWM5 (OUTAUX) SYNC RECT 2 (SR2) SYNC RECT 1 (SR1) PWM4 (OUTD) PWM3 (OUTC) PWM2 (OUTB) PWM1 (OUTA) Figure 36. PWM Timing Diagram Table 58. Register 0x3F—OUTAUX Switching Frequency Setting Bits Name R/W Description [7:6] Reserved R/W Reserved. [5:0] Switching frequency R/W This register sets the switching frequency of the OUTAUX signal. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Frequency (kHz) 0 0 0 0 0 0 48.8 0 0 0 0 0 1 50.4 0 0 0 0 1 0 52.0 0 0 0 0 1 1 53.8 0 0 0 1 0 0 55.8 0 0 0 1 0 1 57.9 0 0 0 1 1 0 60.1 0 0 0 1 1 1 62.5 0 0 1 0 0 0 65.1 0 0 1 0 0 1 67.9 0 0 1 0 1 0 71.0 0 0 1 0 1 1 74.4 0 0 1 1 0 0 78.1 0 0 1 1 0 1 82.2 0 0 1 1 1 0 86.8 0 0 1 1 1 1 91.9 0 1 0 0 0 0 97.6 0 1 0 0 0 1 100.8 0 1 0 0 1 0 104.1 0 1 0 0 1 1 107.7 0 1 0 1 0 0 111.6 |
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