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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32F103xC датащи(PDF) 86 Page - STMicroelectronics |
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STM32F103xC датащи(HTML) 86 Page - STMicroelectronics |
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86 / 123 page  Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 86/123 Doc ID 14611 Rev 7 Figure 42. I/O AC characteristics definition 5.3.14 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 45). Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Figure 43. Recommended NRST pin protection 2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 48. Otherwise the reset will not be taken into account by the device. ai14131 10% 90% 50% tr(IO)out OUTPUT EXT ERNAL ON 50pF Maximum fr equency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%) 10% 50% 90% when loaded by 50pF T tr(IO)out Table 48. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit VIL(NRST) (1) 1. Guaranteed by design, not tested in production. NRST Input low level voltage –0.5 0.8 V VIH(NRST) (1) NRST Input high level voltage 2 VDD+0.5 Vhys(NRST) NRST Schmitt trigger voltage hysteresis 200 mV RPU Weak pull-up equivalent resistor(2) 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order) . VIN VSS 30 40 50 k VF(NRST) (1) NRST Input filtered pulse 100 ns VNF(NRST) (1) NRST Input not filtered pulse 300 ns ai14132c STM32F10xxx RPU NRST(2) VDD Filter Internal Reset 0.1 µF External reset circuit(1) |
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