SMB110 datasheet(29/34 Pages) SUMMIT

29 / 34 page

SMB110

Preliminary Information

Summit Microelectronics, Inc

2099 2.3 3/1/2005

I2C PROGRAMMING INFORMATION

SERIAL INTERFACE

Access to the configuration registers, general-purpose

memory and command and status registers is carried

out over an industry standard 2-wire serial interface

2C). SDA is a bi-directional data line and SCL is a clock

input. Data is clocked in on the rising edge of SCL and

clocked out on the falling edge of SCL. All data transfers

begin with the MSB. During data transfers, SDA must

remain stable while SCL is high. Data is transferred in 8-

bit packets with an intervening clock period in which an

Acknowledge is provided by the device receiving data.

The SCL high period (tHIGH) is used for generating Start

and Stop conditions that precede and end most

transactions on the serial bus. A high-to-low transition of

SDA while SCL is high is considered a Start condition

while a low-to-high transition of SDA while SCL is high is

considered a Stop condition.

The interface protocol allows operation of multiple

devices and types of devices on a single bus through

unique device addressing.

The address byte is

comprised of a 7-bit device type identifier (slave

address). The remaining bit indicates either a read or a

write operation. Refer to Table 1 for a description of the

address bytes used by the SMB110.

The device type identifier for the memory array, the

configuration registers and the command and status

registers are accessible with the same slave address.

The slave address can be can be programmed to any

seven bit number 0000000BIN through 1111111BIN.

WRITE

Writing to the memory or a configuration register is

illustrated in Figures 11 and 12.

A Start condition

followed by the slave address byte is provided by the

host; the SMB110 responds with an Acknowledge; the

host then responds by sending the memory address

pointer or configuration register address pointer; the

SMB110 responds with an acknowledge; the host then

clocks in one byte of data.

For memory and

configuration register writes, up to 15 additional bytes of

data can be clocked in by the host to write to

consecutive addresses within the same page.

After the last byte is clocked in and the host receives an

Acknowledge, a Stop condition must be issued to initiate

the nonvolatile write operation.

READ

The address pointer for the non-volatile configuration

registers and memory registers as well as the volatile

command and status registers must be set before data

can be read from the SMB110. This is accomplished by

issuing a dummy write command, which is a write

command that is not followed by a Stop condition. A

dummy write command sets the address from which

data is read. After the dummy write command is issued,

a Start command followed by the address byte is sent

from the host. The host then waits for an Acknowledge

and then begins clocking data out of the slave device.

The first byte read is data from the address pointer set

during the dummy write command. Additional bytes can

be clocked out of consecutive addresses with the host

providing an Acknowledge after each byte. After the

data is read from the desired registers, the read

operation is terminated by the host holding SDA high

during the Acknowledge clock cycle and then issuing a

Stop condition. Refer to Figure 13 for an illustration of

the read sequence.

CONFIGURATION REGISTERS

The configuration registers are grouped with the general-

purpose memory.

GENERAL-PURPOSE MEMORY

The

96-byte

general-purpose

memory

block

segmented into two continuous independently lockable

blocks. The first 48-byte memory block begins at register

address pointer A0HEX and the second memory block

begins at the register address pointer C0HEX; see Table

1. Each memory block can be locked individually by

writing to a dedicated register in the configuration

memory space.

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