ADIS16260/ADIS16265

Rev. PrB | Page 14 of 19

OPERATIONAL CONTROL

Internal Sample Rate

The internal sample rate defines how often data output variables

are updated, independent of the rate at which they are read out

on the SPI port. The SMPL_PRD register controls the

ADIS16260/ADIS16265 internal sample rate and has two parts:

a selectable time base and a multiplier. When SMPL_PRD is

greater than zero, the sample period can be calculated using the

following equation:

where:

When SMPL_PRD[7:0] = 0x00, the internal sample setting is

2048SPS. Since this mode bypasses an internal filtering network,

it will result in a total noise increase of approximately 25%. This

SENS_AVG register provides opportunity for noise reduction.

The default value is the maximum 256 samples per second, and

the contents of this register are nonvolatile.

Table 15. SMPL_PRD Register Definition

Address

Default

Format

Access

0x37, 0x36

0x0001

N/A

R/W

Table 16. SMPL_PRD Bit Descriptions

Bit

Description

15:8

Not used

7

Time base, 0 = 1.953 ms, 1 = 60.54 ms

6:0

Multiplier

The following is an example calculation of the sample period for

the ADIS16260/ADIS16265:

If SMPL_PRD = 0x0007, B7…B0 = 00000111

The sample rate setting has a direct impact on the SPI data rate

capability. For sample rates of 64 SPS and above, the SPI SCLK

can run at a rate up to 2.5 MHz. For sample rates below 64 SPS,

the SPI SCLK can run at a rate up to 1 MHz.

The sample rate setting also affects the power dissipation. When

the sample rate is set below 64 SPS, the power dissipation reduces

by a factor of 60%. The two different modes of operation offer a

system-level trade-off between performance (sample rate, serial

transfer rate) and power dissipation.

Power Management

In addition to offering two different performance modes for

power optimization, the ADIS16260/ADIS16265 offer a

programmable shutdown period. Writing the appropriate sleep

time to the SLP_CNT register shuts the device down for the

specified time. The following example provides an illustration

of this relationship:

B7 … B0 = 00000110

Sleep period = 3 sec

After completing the sleep period, the ADIS16260/ADIS16265

return to normal operation. If measurements are required

before sleep period completion, the ADIS16260/ADIS16265 can

be awakened by putting the CS line in a zero logic state.

Otherwise, the CS line must be kept high to maintain sleep

mode.

Table 17. SLP_CNT Register Definition

Address

Default

Format

Access

0x3B, 0x3A

0.5 sec

0x0000

Binary

R/W

Table 18. SLP_CNT Bit Descriptions

Bit

Description

15:8

Not used

7:0

Data bits

Analog Bandwidth

The analog bandwidth of the ADIS16260/ADIS16265 is 50 Hz.

This bandwidth can be reduced by placing an external capacitor

across the RATE and FILT pins. In this case, the analog

bandwidth can be calculated using the following equation:

where:

CIN = 0.0377μF when SENS_AVG[7] = 0

CIN = 0.0047μF when SENS_AVG[7] = 1

Digital Filtering

The ADIS16260/ADIS16265 GYRO_OUT signal path has a

nominal analog bandwidth of 50 Hz. The ADIS16260 provides a

Bartlett Window FIR filter for additional noise reduction on all of

the output data registers. The SENS/AVG register stores the

number of taps in this filter in seven power-of-two step sizes

simple step: write the appropriate M factor to the assigned bits

in the SENS/AVG register. The bit assignments are listed in

Table 20. The following equation offers a frequency response

relationship for this filter:

)

sin(

)

sin(

)

(

)

(

)

(

2

S

S

A

A

B

t

f

N

t

f

N

f

H

f

H

f

H





















