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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9267EBZ датащи(PDF) 15 Page - Analog Devices |
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AD9267EBZ датащи(HTML) 15 Page - Analog Devices |
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15 / 24 page  AD9267 Rev. 0 | Page 15 of 24 The second mode bypasses the clock multiplier circuitry and allows the clock to be directly sourced. This mode enables the user to source a very high quality clock directly to the Σ-Δ modulator. Sourcing the clock directly may be necessary in demanding applications that require the lowest possible output noise. Refer to Figure 18, which shows the degradation in SNR performance for the various PLL settings. In either case, when using the on-chip clock multiplier or sourcing the high speed clock directly, it is necessary that the clock source have low jitter to maximize the Σ-Δ modulator noise performance. High speed, high resolution ADCs and modulators are sensitive to the quality of the clock input. As jitter increases, the SNR performance of the AD9267 degrades from that specified in Table 2. The jitter inherent to the part due to the PLL root sum squares with any external clock jitter, thereby degrading performance. To prevent jitter from dominating the performance of the AD9267, the input clock source should be no greater than 1 ps rms of jitter. The CLK± inputs are self-biased to 450 mV (see Figure 21); if dc-coupled, it is important to maintain the specified 450 mV input common-mode voltage. Each input pin can safely swing from 200 mV p-p to 1 V p-p single-ended about the 450 mV common-mode voltage. The recommended clock inputs are CMOS or LVPECL. The specified clock rate of the Σ-Δ modulator, fMOD, is 640 MHz. The clock rate possesses a direct relationship with the available input bandwidth of the ADC. Bandwidth = fMOD ÷ 64 In either case, using the on-chip clock multiplier to generate the Σ-Δ modulator clock rate or directly sourcing the clock, any deviation from 640 MHz results in a change in input bandwidth. The input range of the clock is limited to 640 MHz ± 5%. Direct Clocking The default configuration of the AD9267 is for direct clocking where the PLL is bypassed. Figure 38 shows one preferred method for clocking the AD9267. A low jitter clock source is converted from a single-ended signal to a differential signal using an RF transformer. The back-to-back Schottky diodes across the secondary side of the transformer limits clock excursions into the AD9267 to approximately 0.8 V p-p differen- tial. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9267 while preserving the fast rise and fall times of the signal, which are critical to achieving low jitter. CLOCK INPUT XFMR MINI-CIRCUITS TC1-1-13M+, 1:1 SCHOTTKY DIODES: HSM2812 50 Ω CLK+ CLK– 0.1µF 0.1µF ADC AD9267 0.1µF 0.1µF Figure 38. Transformer-Coupled Differential Clock If a differential clock is not available, the AD9267 can be driven by a single-ended signal into the CLK+ terminal with the CLK− terminal ac-coupled to ground. Figure 39 shows the circuit configuration. SCHOTTKY DIODES: HSM2812 50 Ω CLK+ CLK– 0.1µF 0.1µF ADC AD9267 CLOCK INPUT Figure 39. Single-Ended Clock Another option is to ac couple a differential LVPECL signal to the sample clock input pins, as shown in Figure 40. The AD951x family of clock drivers is recommended because it offers excellent jitter performance. 100 Ω 240 Ω 240 Ω 50 Ω1 150 Ω RESISTORS ARE OPTIONAL. 50 Ω1 CLK+ CLK– 0.1µF 0.1µF ADC AD9267 CLOCK INPUT CLOCK INPUT 0.1µF 0.1µF CLK AD951x LVPECL DRIVER CLK Figure 40. Differential LVPECL Sample Clock Internal PLL Clock Distribution The alternative clocking option available on the AD9267 is to apply a low frequency reference clock and use the on-chip clock multiplier to generate the high frequency fMOD rate. The internal clock architecture is shown in Figure 41. PHASE DETECTOR DIVIDER PLLMULT 0x0A[5:0] CLK± MODULATOR CLOCK 640MSPS PLLENABLE 0x09[2] ÷N LOOP FILTER VCO PLL ÷2 Figure 41. Internal Clock Architecture The clock multiplication circuit operates such that the VCO outputs a frequency, fVCO, equal to the reference clock input multiplied by N fVCO = (CLK±) × (N) where N is the PLL multiplication (PLLMULT) factor. The Σ-Δ modulator clock frequency, fMOD, is equal to fMOD = fVCO ÷ 2 |
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