AD9267EBZ datasheet(6/24 Pages) AD

6 / 24 page

AD9267

Rev. 0 | Page 6 of 24

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, unless otherwise noted.

Table 4.

Parameter1

Conditions/Comments

Temp

Min

Typ

Max

Unit

CLOCK INPUT PARAMETERS

Using clock multiplier

Input CLK Rate

Full

160

MSPS

CLK± Period

Full

6.25

33.3

CLK± Duty Cycle

Full

CLOCK INPUT PARAMETERS

Direct clocking

Conversion Rate

Full

608

640

672

MSPS

CLK± Period

Full

1.48

1.5625

1.72

CLK± Duty Cycle

Full

DATA OUTPUT PARAMETERS

Data Propagation Delay (tPD)2

Full

160

510

840

DCO± Propagation Delay (tDCO)

Full

-60

268

570

DCO± to Data Skew (tSKEW)

Full

180

200

280

Aperture Uncertainty (Jitter, tJ)

Full

ps rms

WAKE-UP TIME

Power-Down Power

25°C

Μs

Standby Power

25°C

μs

Sleep Power

25°C

μs

OUT-OF-RANGE RECOVERY TIME

25°C

100

SERIAL PORT INTERFACE3

SCLK Period (tSCLK)

Full

SCLK Pulse Width High Time (tSHIGH)

Full

SCLK Pulse Width Low Time (tSLOW)

Full

SDIO to SCLK Set-Up Time (tSDS)

Full

SDIO to SCLK Hold Time (tSDH)

Full

CSB to SCLK Set-Up Time (tSS)

Full

CSB to SCLK Hold Time (tSH)

Full

1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

2 Output propagation delay is measured from CLK± 50% transition to data D0±x to D3±x 50% transition, with 5 pF load.

3 See Figure 42 and the Serial Port Interface (SPI) section.

Timing Diagram

CLK±

DCO±

D0±x TO D3±x

tPD

tDCO

tSKEW

Figure 2. Timing Diagram

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