AD9267EBZ datasheet(14/24 Pages) AD

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AD9267

Rev. 0 | Page 14 of 24

Differential Input Configurations

Optimum performance can be achieved by driving the AD9267

in a differential input configuration. The ADA4937-2 differential

driver provides excellent performance and a flexible interface to

the ADC. The output common-mode voltage of the ADA4937-2 is

easily set by connecting AVDD to the VOCMx pin of the ADA4937-2

(see Figure 33). The noise and linearity of the ADA4937-2 needs

important consideration because the system performance may

be limited by the ADA4937-2.

200Ω

60.4Ω

49.9Ω

50Ω

SIGNAL

SOURCE

2V p-p

60.4

VIN–x

VIN+x

0.1µF

+5V

–5V

ADA4937-2

VOCM2

AD9267

0.1µF

AVDD

+1.8V

Figure 33. Differential Input Configuration Using the ADA4937-2

For frequencies offset from dc, where SNR is a key parameter,

differential transformer coupling is the recommended input

configuration. An example is shown in Figure 34. The center

tap of the secondary winding of the transformer is connected to

AVDD to bias the analog input.

The signal characteristics must be considered when selecting a

transformer. Most RF transformers saturate at frequencies

below a couple of megahertz (MHz), and excessive signal power

can cause core saturation, which leads to distortion.

50Ω

SIGNAL

SOURCE

2V p-p

1:1

50Ω

VIN–x

VIN+x

0.1µF

AVDD

AD9267

Figure 34. Differential Transformer Configuration

Voltage Reference

A stable and accurate 0.5 V voltage reference is built into the

AD9267. The reference voltage should be decoupled to minim-

ize the noise bandwidth using a 10 μF capacitor. The reference

is used to generate a bias current into a matched resistor such

that when used to bias the current in the feedback DAC, a

voltage of AVDD − 0.5 V is developed at the internal side of the

input resistors (see Figure 35). The current bias circuit should

also be decoupled on the CFILT pin with a 10 μF capacitor. For

this reason, the VREF voltage should always be 0.5 V.

AVDD

AVDD – 0.5V

CFILT

AVDD – 0.5V

500Ω

TO LOOP

FILTER

STAGE 2

500Ω

VIN+x

VCM =AVDD

VIN p-p = 2V

VIN–x

500Ω

10kΩ

10µF

0.5V

VREF

10µF

REF

Figure 35. Voltage Reference Loop

Internal Reference Connection

To minimize thermal noise, the internal reference on the AD9267

is an unbuffered 0.5 V. It has an internal 10 kΩ series resistor,

which, when externally decoupled with a 10 μF capacitor, limits

the noise (see Figure 36). Do not use the unbuffered reference

to drive any external circuitry. The internal reference is used by

default and when Serial Register 0x18[6] is reset.

10kΩ

2.85kΩ

8.5kΩ

3.5kΩ

0.5V

TO CURRENT

GENERATOR

10µF

Figure 36. Internal Reference Configuration

External Reference Operation

If an external reference is desired, the internal reference can be

disabled by setting Serial Register 0x18[6] high. Figure 37 shows

an application using the ADR130B as a stable external reference.

0.5V

ADR130B

TO CURRENT

GENERATOR

0.1µF

10µF

AVDD

10kΩ

Figure 37. External Reference Configuration

CLOCK INPUT CONSIDERATIONS

The AD9267 offers two modes of sourcing the ADC sample

clock (CLK+ and CLK−). The first mode uses an on-chip clock

multiplier that accepts a reference clock operating at the lower

input frequency. The on-chip phase-locked loop (PLL) then

multiplies the reference clock up to a higher frequency, which is

then used to generate all the internal clocks required by the Σ-Δ

modulator.

The clock multiplier provides a high quality clock that meets

the performance requirements of most applications. Using the

on-chip clock multiplier removes the burden of generating and

distributing the high speed clock.

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