AS4C4M4DG-7SLASHXT datasheet(7/19 Pages) AUSTIN

номер детали	AS4C4M4DG-7/XT

подробное описание детали	4M x 4 CMOS DRAM WITH FAST PAGE MODE, 5 VOLT

PDF	19 Pages

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производитель	AUSTIN [Austin Semiconductor]

домашняя страница	http://www.austinsemiconductor.com

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16 Me

16 Meg FPM DRAM

g FPM DRAM

AS4C4M4

AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.

AS4C4M4

Rev. 1.1 06/05

Austin Semiconductor, Inc.

READ CYCLE

NOTES (continued):

8. Either t

RCH or tRRH must be satisfied for a read cycle.

9. These parameters are referenced to CAS\ falling edge in early write cycles and to W\ falling edge in read-modify-write

cycles.

10. Operation within the t

RAD(MAX) limit insures that tRAC(MAX) can be met. tRAD(MAX) is specified as a reference point only.

If t

RAD is greater than the specified tRAS(MAX) limit, then access time is controlled by tAA.

11. These specifications are applied in the test mode.

12. In test mode read cycle, the value of t

RAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters

should be specified in test mode cycles by adding the above value to the specified value in this data sheet.

13. If t

RASS > 100 us, then RAS\ precharge time must use tRPS instead of tRP.

14. For RAS\-only refresh and burst CAS\-before-RAS\ refresh mode, 2048 cycles of burst refresh must be executed within

32ms before and after self refresh, in order to meet refresh specification.

15. For distributed CAS\-before-RAS\ with 15.6us interval CAS\-before-RAS\ refresh should be executed with in 15.6us

immediately before and after self refresh in order to meet refresh specification.

AS4C4M4DG-7/XT датащи(PDF) 7 Page - Austin Semiconductor