TSB41BA3DPFP datasheet(9/59 Pages) TI

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TSB41BA3D

www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009

Table 1. Terminal Functions (continued)

TERMINAL

I/O

DESCRIPTION

PFP

NAME

TYPE

NO.

PLLGND

Supply

25, 28

–

PLL circuit ground terminals. These terminals must be tied together to the low-impedance

circuit board ground plane.

PLLVDD-CORE

Supply

29, 30

–

PLL core circuit power terminals. A combination of high-frequency decoupling capacitors

near each terminal is suggested, such as paralleled 0.1

µF and

0.001

µF. An additional 1-µF capacitor is required for voltage regulation. The

PLLVDD-CORE terminals must be separate from the DVDD-CORE terminals. These supply

terminals are separated from the DVDD-CORE, DVDD-3.3, PLLVDD-3.3, and AVDD-3.3

terminals internal to the device to provide noise isolation.

PLLVDD-3.3

Supply

–

PLL 3.3-V circuit power terminal. A combination of high-frequency decoupling capacitors

near the terminal are suggested, such as paralleled 0.1

µF and

0.001

µF. Lower frequency 10-µF filtering capacitors are also recommended. This supply

terminal is separated from the DVDD-CORE, DVDD-3.3, PLLVDD-CORE, and AVDD-3.3

terminals internal to the device to provide noise isolation. The DVDD-3.3 terminals must be

tied together at a low-impedance point on the circuit board. The PLLVDD-3.3, AVDD-3.3,

and DVDD-3.3 terminals must be tied together with a low dc impedance connection.

RESET

CMOS

Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup

resistor to VDD is provided so only an external delay capacitor is required for proper

power-up operation (see power-up reset in the Application Information section). The

RESET terminal also incorporates an internal pulldown which is activated when the PD

input is asserted high. This input is otherwise a standard logic input, and can also be driven

by an open-drain-type driver.

Bias

–

Current setting resistor terminals. These terminals are connected to a precision external

resistance to set the internal operating currents and cable driver output currents. A

resistance of 6.34 k

Ω ±1% is required to meet the IEEE Std 1394-1995 output voltage

limits.

CMOS

Test control input. This input is used in the manufacturing test of the TSB41BA3D. For

normal use, this terminal must be pulled low either through a 1-k

Ω resistor to GND or

directly to GND.

SLPEN

CMOS

Automotive sleep mode enable input. This terminal enables the automotive sleep mode.

When deasserted (logic-low), normal 1394.b functionality is maintained.

CMOS

Test control input. This input is used in the manufacturing test of the TSB41BA3D. For

normal use this terminal must be pulled low either through a 1-k

Ω resistor to GND or

directly to GND.

S2_PC0

CMOS

Port sleep/mode selection terminals 2-0 and power-class programming. On hardware reset,

S1_PC1

this terminal when used with the other five selection terminals allows the user to select the

S0_PC2

speed and mode of the ports. See Table 2. Depending on the selection, these inputs can

set the default value of the power class indicated during self-ID.

Programming is done by tying the terminals high through a 1-k

Ω or smaller resistor or by

tying directly to ground through a 1-k

Ω or smaller resistor. Bus holders are built into these

terminals.

CMOS

Port sleep/mode selection terminal 3. On hardware reset, this terminal when used with the

other five selection terminals allows the user to select the speed and mode of the ports.

See Table 2. Programming is done by tying the terminals high through a 1-k

Ω or smaller

resistor or by tying directly to ground through a 1-k

Ω or smaller resistor. A bus holder is

built into this terminal.

CMOS

Port sleep/mode selection terminal 4. On hardware reset, this terminal when used with the

other five selection terminals allows the user to select the speed and mode of the ports.

See Table 2. Programming is done by tying the terminals high through a 1-k

Ω or smaller

resistor or by tying directly to ground through a 1-k

Ω or smaller resistor. A bus holder is

built into this terminal.

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