TSB41BA3DPFP datasheet(43/59 Pages) TI

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SYSCLK

ISO

(high)

(a)

(c)

(b)

CTL0

D0–D7

LREQ

LPS

(d)

tCLK_ACTIVATE

CTL1

7 Cycles

TSB41BA3D

www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009

After the interface has been reset, or reset and then disabled, the interface is initialized and restored to normal

operation when LPS is reasserted by the LLC. Figure 21 shows the timing for interface initialization.

Figure 21. Interface Initialization

The sequence of events for initialization of the PHY-LLC is as follows:

a. LPS reasserted. After the interface has been in the reset or disabled state for at least the minimum tRESTORE

time, the LLC causes the interface to be initialized and restored to normal operation by reasserting the LPS

signal. (In Figure 21, the interface is shown in the disabled state with PCLK inactive. However, the interface

initialization sequence described here is also executed if the interface is merely reset but not yet disabled.)

b. PCLK activated. If the interface is disabled, then the PHY reactivates its PCLK output when it detects that

LPS has been reasserted. If the PHY has entered a low-power state, then it takes between 5.3 ms and 7.3

ms for PCLK to be restored; if the PHY is not in a low-power state, then the PCLK is restored within 60 ns.

The PCLK output is a 50% duty cycle square wave with a frequency of 49.152 MHz ±100 ppm (period of

20.345 ns). During the first 7 cycles of PCLK, the PHY continues to drive the CTL and D terminals low. The

LLC is also required to drive its CTL and D outputs low for one of the first 6 cycles of PCLK but otherwise to

place its CTL and D outputs in the high-impedance state. The LLC continues to drive its LREQ output low

during this time.

c. Receive indicated. On the eighth PCLK cycle following reassertion of LPS, the PHY asserts the receive state

on the CTL lines and the data-on indication (all 1s) on the D lines for one or more cycles.

d. Initialization complete. The PHY asserts the idle state on the CTL lines and logic 0 on the D lines. This

indicates that the PHY-LLC interface initialization is complete and normal operation can commence. The

PHY now accepts requests from the LLC via the LREQ line.

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