TSB41BA3DPFP datasheet(31/59 Pages) TI

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TSB41BA3D

www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009

It is recommended that the RHB and gap-count register only be updated by PHY configuration packets. The

TSB41BA3D is 1394a- and 1394b-compliant, and therefore, both the reception and transmission of PHY

configuration packets cause the RHB and gap-count register to be loaded, unlike older IEEE Std

1394-1995-compliant PHYs which decode only received PHY configuration packets.

The gap-count register is set to the maximum value of 63 after two consecutive bus resets without an intervening

write to the gap-count register, either by a write to PHY register 1 or by a PHY configuration packet. This

mechanism allows a PHY configuration packet to be transmitted and then a bus reset to be initiated so as to

verify that all nodes on the bus have updated their RHBs and gap-count register values, without having the

gap-count register set back to 63 by the bus reset. The subsequent connection of a new node to the bus, which

initiates a bus reset, then causes the gap-count register of each node to be set to 63. Note, however, that if a

subsequent bus reset is instead initiated by a write to register 1 to set the IBR bit, then all other nodes on the bus

have their gap-count register values set to 63, while this node's gap-count register remains set to the value just

loaded by the write to PHY register 1.

Therefore, in order to maintain consistent gap-count registers throughout the bus, the following rules apply to the

use of the IBR bit, RHB, and gap-count register in PHY register 1:

• Following the transmission of a PHY configuration packet, a bus reset must be initiated in order to verify that

all nodes have correctly updated their RHBs and gap-count register values, and to ensure that a subsequent

new connection to the bus causes the gap-count register to be set to 63 on all nodes in the bus. If this bus

reset is initiated by setting the IBR bit to 1, then the RHB and gap-count register must also be loaded with the

correct values consistent with the just-transmitted PHY configuration packet. In the TSB41BA3D, the RHB

and gap-count register have been updated to their correct values on the transmission of the PHY

configuration packet and so these values can first be read from register 1 and then rewritten.

• Other than to initiate the bus reset, which must follow the transmission of a PHY configuration packet,

whenever the IBR bit is set to 1 in order to initiate a bus reset, the gap-count register value must also be set

to 63 so as to be consistent with other nodes on the bus, and the RHB must be maintained with its current

value.

• The PHY register 1 must not be written to except to set the IBR bit. The RHB and gap-count register must not

be written without also setting the IBR bit to 1.

• To avoid these problems, all bus resets initiated by software must be initiated by writing the ISBR bit (bit 1

PHY register 0101b). Care must be taken to not change the value of any of the other writeable bits in this

by means of the PHY configuration packet, which changes all nodes to the same gap count.

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