TPS2202AI

DUAL-SLOT PC CARD POWER-INTERFACE SWITCH

WITH RESET FOR SERIAL PCMCIA CONTROLLER

SLVS123A – SEPTEMBER 1995 – REVISED JUNE 1998

6

POST OFFICE BOX 655303

POST OFFICE BOX 1443

PARAMETER MEASUREMENT INFORMATION

LOAD CIRCUIT

CL

ton

VOLTAGE WAVEFORMS

VI(12V)

GND

50%

90%

VDD

GND

LATCH

VO(xVPP)

Vpp

LOAD CIRCUIT

CL

VCC

ton

toff

VOLTAGE WAVEFORMS

VI(5V)

GND

50%

90%

10%

VDD

GND

LATCH

VO(xVCC)

10%

toff

Figure 1. Test Circuits and Voltage Waveforms

Table of Timing Diagrams

FIGURE

Serial-Interface Timing

2

xVCC Propagation Delay and Rise Time With 1-

µF Load, 3.3-V Switch

3

xVCC Propagation Delay and Fall Time With 1-

µF Load, 3.3-V Switch

4

xVCC Propagation Delay and Rise Time With 100-

µF Load, 3.3-V Switch

5

xVCC Propagation Delay and Fall Time With 100-

µF Load, 3.3-V Switch

6

xVCC Propagation Delay and Rise Time With 1-

µF Load, 5-V Switch

7

xVCC Propagation Delay and Fall Time With 1-

µF Load, 5-V Switch

8

xVCC Propagation Delay and Rise Time With 100-

µF Load, 5-V Switch

9

xVCC Propagation Delay and Fall Time With 100-

µF Load, 5-V Switch

10

xVPP Propagation Delay and Rise Time With 1-

µF Load, 12-V Switch

11

xVPP Propagation Delay and Fall Time With 1-

µF Load, 12-V Switch

12

xVPP Propagation Delay and Rise Time With 100-

µF Load, 12-V Switch

13

xVPP Propagation Delay and Fall Time With 100-

µF Load, 12-V Switch

14

NOTE A: Data is clocked in on the positive leading edge of the clock. The latch should occur before next positive leading edge of the

clock. For definition of D0 to D8, see the control logic table.

DATA

LATCH

CLOCK

D8

D7

D6

D5

D4

D3

D2

D1

D0

Figure 2. Serial-Interface Timing