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TMP320C40KGDC, SMJ320C40KGDC, TMP320C40KGDCT, SMJ320C40KGDCT

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

KNOWN GOOD DIES

SGUS024B – MARCH 1997 – REVISED APRIL 2000

1

POST OFFICE BOX 1443

– Military (M) – 55

°C to 125°C

– Commercial (C) – 25

°C to 85°C

– Commercial (L) 0

°C to 70°C

Signal Processor (DSP)

– ’C40-50:

40-ns Instruction Cycle Time:

50 MFLOPS, 25 MIPS, 275 MOPS,

320 MBps

– ’C40-40:

50-ns Instruction Cycle Time:

40 MFLOPS, 20 MIPS, 220 MOPS,

256 MBps

Coprocessor

IEEE-745 Floating-Point Format

32-Bit Integer Multipliers

14 Control Registers, and 2 Timers

(JTAG)

Buses Supporting Shared Memory Systems

and High Data-Rate, Single-Cycle

Transfers:

– High Port-Data Rate of 100 MBytes/s

(Each Bus)

– 16G-Byte Continuous

Program/Data/Peripheral Address Space

– Memory-Access Request for Fast,

Intelligent Bus Arbitration

– Separate Address-, Data-, and

Control-Enable Pins

– Four Sets of Memory-Control Signals

Support Different Speed Memories in

Hardware

Performance Implanted CMOS (EPIC

™)

Technology by Texas Instruments (TI

™)

Coprocessor Buses for Support of Massive

Concurrent Input/Output (I/O) of Program

and Data Throughput, Maximizing

Sustained Central Processing Unit (CPU)

Performance

Dual-Access/Single-Cycle RAM for

Increased Memory-Access Performance

– 512-Byte Instruction Cache

– 8K Bytes of Single-Cycle Dual-Access

Program or Data RAM

– ROM-Based Bootloader Supports

Program Bootup Using 8-, 16-, or 32-Bit

Memories Over Any One of the

Communications Ports

description

The TMP / SMJ320C40KGD DSP is a 32-bit, floating-point processor manufactured in 0.72-

µm, double-level

metal CMOS technology. It is the fourth generation of DSPs from Texas Instruments, and it is the world’s first

DSP designed for parallel processing. The on-chip parallel processing capabilities of the ’C40 make the

floating-point performance required by many applications achievable and cost-effective.

The TMP / SMJ320C40 is the first DSP with on-chip communication ports for processor-to-processor

communication using simple communication software with no external hardware. This allows connectivity with

no external glue logic. The communication ports remove I/O bottlenecks, and the independent smart-DMA

coprocessor is able to handle the CPU I/O requirements.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Copyright

© 2000, Texas Instruments Incorporated

† IEEE Standard 1149.1–1990 Standard Test-Access Port and Boundary-Scan Architecture

EPIC and TI are trademarks of Texas Instruments Incorporated.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.