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TAS1020B датащи(PDF) 90 Page - Texas Instruments |
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TAS1020B датащи(HTML) 90 Page - Texas Instruments |
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90 / 114 page ![]() A–22 A.5.2.2 DMA Time Slot Assignment Register (High Byte) (DMATSH1 – Address FFEFh) (DMATSH0 – Address 0xFFE9) Bit 7 6 5 4 3 2 1 0 Mnemonic BPTS1 BPTS0 TSL13 TSL12 TSL11 TSL10 TSL9 TSL8 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:6 BPTS(1:0) Bytes per time slot The bytes per time slot bits are used to define the number of bytes to be transferred for each time slot supported by this DMA channel. 00b = 1 byte, 01b = 2 bytes, 10b = 3 bytes, 11b = 4 bytes 5:0 TSL(13:8) Time slot assignment The DMA time slot assignment bits are set to 1 by the MCU to define the codec port interface time slots supported by this DMA channel. A.5.2.3 DMA Control Register (DMACTL1 – Address FFEEh) (DMACTL0 – Address FFE8h) Bit 7 6 5 4 3 2 1 0 Mnemonic DMAEN HSKEN — — EPDIR EPNUM2 EPNUM1 EPNUM0 Type R/W R/W R R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7 DMAEN DMA enable The DMA enable bit is set to a 1 by the MCU to enable this DMA channel. Before enabling the DMA channel, all other DMA channel configuration bits must be set to the desired value. 6 HSKEN Handshake enable This bit is relevant for BULK data transfer in the OUT direction through DMA. MCU must set this bit to a 1 to enable the handshake mode for the data transfer. If MCU sets this bit, MCU has to enable DMA for each received BULK OUT packet. DMA, once enabled, transfers the BULK OUT packet to the C-port, disables itself and generates an interrupt to the MCU. If MCU clears this bit, DMA handles the BULK OUT data transfer to the C-port without MCU intervention. For more details, see Section 2.2.7.3.3. 5 — Reserved Reserved for future use 4 — Reserved Reserved for future use 3 EPDIR USB endpoint direction The USB endpoint direction bit controls the direction of data transfer by this DMA channel. The MCU should set this bit to a 1 to configure this DMA channel to be used for a USB IN endpoint. The MCU must clear this bit to a 0 to configure this DMA channel to be used for a USB OUT endpoint. 2:0 EPNUM(2:0) USB endpoint number The USB endpoint number bits are set by the MCU to define the USB endpoint number supported by this DMA channel. Keep in mind that endpoint 0 is always used for the control endpoint, which is serviced by the MCU and not a DMA channel. 001b = Endpoint 1, 010b = Endpoint 2, …, 111b = Endpoint 7, 000b = Illegal A.5.2.4 DMA Current Buffer Content Register (Low-Byte) (DMABCNT1L – Address FFF3h) (DMABCNT0L– Address FFEBh) Bit 7 6 5 4 3 2 1 0 Mnemonic Size 7 Size 6 Size 5 Size 4 Size 3 Size 2 Size 1 Size 0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 Size(7:0) Buffer content This register shows the buffer content (bytes) for an ISO OUT endpoint. This register is updated every SOF and is stable for the following USB frame, during which the MCU can read it to implement USB audio synchronization. |
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