TAS1020B datasheet(46/114 Pages) TI

46 / 114 page

2–32

If the C/NT bit in the appropriate MCU special function register (SFR) for a given timer is cleared to enable a timer

function, or if the timer/counter interrupt is masked off by clearing the appropriate ET bit in the MCU interrupt enable

For the external trigger input for timer 2, it is necessary to clear bit EXEN2 in the MCU timer/counter 2 control register

T2CON if this input is to be used as a general-purpose input.

2.2.11.1.4 MCU Read/Write Pulse Alternate Function

The TAS1020B provides the capability of replacing the internal MCU core with an in-circuit emulator (ICE) for firmware

development. When in the external MCU mode of operation (EXTEN = 1), port 3 bits P3.7 and P3.6 respectively are

used to input the ICE-generated memory read and write pulses so that the ICE can access the memory-mapped

resources internal to the TAS1020B (but not those resources internal to the MCU core itself). When in the internal

MCU mode, P3.6 and P3.7 output the external memory write and read pulses respectively from the MCU core, and

can be used as troubleshooting aids. P3.6 and P3.7 cannot be used as GPIO resources.

2.2.11.2 Port 1 GPIO Bits

Port 1 has two bits that have alternate input functionality – P1.0 and P1.1. The alternate function serviced by these

inputs is timer 2. P1.0 provides the external event clock for timer 2 and P1.1 provides the external trigger. These

alternate functions and the conditions under which these two bits can be used as GPIO bits are discussed in Section

2.2.11.1.3.

Port 1 provides no alternate output functionality.

2.2.12 DMA Controller

The TAS1020B provides two DMA channels for transferring data between the USB endpoint buffers and the codec

port interface. The DMA channels are provided to support the streaming of data for USB isochronous or bulk OUT

endpoints only. Each DMA channel can be programmed to service one isochronous endpoint. The endpoint number

and direction are programmable using the DMA channel control register provided for each DMA channel.

For the two AC ’97 modes supported by the TAS020A, one DMA channel can be assigned to support bulk OUT

transactions and the second DMA channel assigned to support isochronous IN transactions. An example would be

downloading an AC3 file for storage via a bulk OUT transaction while, at the same time, supporting an isochronous

recording session. For all formats and protocols other than AC ’97, however, if a DMA channel is assigned to support

bulk OUT transactions, it can be the only DMA channel active. If, for example, DMA channel 0 is assigned to support

bulk OUT transactions in the General Purpose mode, then DMA channel 1 cannot be assigned to support bulk OUT

or isochronous transactions.

Section 2.2.7.3.3 provides more detail on DMA-supported bulk OUT transactions

The codec port interface time slots to be serviced by a particular DMA channel must also be programmed. For

example, an AC ’97 mode stereo speaker application uses time slots 3 and 4 for audio playback. Therefore, the DMA

channel used to move the audio data to the codec port interface must set time slot assignment bits 3 and 4 to a 1.

Each DMA channel is capable of being programmed to transfer data for time slots 0 through 13 using the two DMA

channel time slot assignment registers provided for each DMA channel.

The number of bytes to be transferred for each time slot is also programmable. The number of bytes used must be

set based on the desired audio data format.

2.2.13 Codec Port Interface

The codec port interface is a configurable serial interface used to transfer data between the TAS1020B IC and a codec

device. The serial protocol and formats supported include AC ’97 1.0, AC ’97 2.0, and several I2S modes. In addition,

a general-purpose mode is provided that can be configured to various user defined serial interface formats.

Configuration of the interface is accomplished using the four codec port interface configuration registers: CPTCNF1,

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