TAS1020B datasheet(38/114 Pages) TI

38 / 114 page

2–24

•

At the same time that the DMA engine reinitializes itself to receive the next input device frame, the UBM

has noted the clearing of the NACK flag in IEPDCNTX/Y. When this occurs, the UBM knows that one or more

complete frames reside in the circular buffer, starting at the address pointed to by the read buffer, and that

the integer number of frames comprise a total of DCNTX/Y samples. When the USB SOF event occurs, the

UBM is thus prepared and can respond to the USB isochronous in transaction when it occurs. As the UBM

retrieves data during the isochronous in transaction, it updates the read pointer by one count for each byte

retrieved. When DCNTX/Y samples have been output, the NACK bit in IEPDCNTX/Y is set back to logic

1 and the isochronous transaction is terminated. The UBM now awaits the clearing of the NACK bit in

IEPDCNTX/Y and the occurrence of the next USB SOF event, at which time the process repeats. The UBM

now continues to alternate (ping pong) between the data count and NACK flag value in register IEPDCNTX

and the data count and NACK flag value in register IEPDCNTY until the DMA process is terminated by the

MCU.

•

If an isochronous in token is received when there is no new data to be output (the NACK flag bits in both

IEPDCNTX and IEPDCNTY registers are at logic 1), the UBM will respond to the isochronous in request

with a NULL packet.

2.2.8

Microcontroller Unit

The TAS1020B chip contains an 8-bit microcontroller core for control and supervisory functions. The microcontroller

core used is based on the industry standard 8052. It is software compatible (including instruction execution times)

with the industry standard 8052AH and 8052BH discrete devices, having all their core features plus the additional

features corresponding to standard 8052 / 8032 / 80C52BH / 80C32BH / 87C52 parts – except the ONCE mode and

program lock are not supported.

The MCU core has three 16-bit timer/counter units and a full-duplex serial port (UART). The timer/counter units and

the UART are made available via the port 3 bits; thus some of the port 3 bits have dual functionality assignments in

accordance with the 80C51 family of microcontrollers (see Section 2.2.11 for more detail on the dual functionality of

port 3).

2.2.9

External MCU Mode Operation

An external MCU mode of operation is provided for firmware development using an in-circuit emulator (ICE). The

external MCU mode is selected by setting pin EXTEN on the TAS1020B high. When the external MCU mode is

selected, the internal 8052 MCU core of the TAS1020B is disabled. Also in the external MCU mode, the GPIO ports

are used for the external MCU data, address, and control signals. Refer to section 1.7, Terminal Functions – External

MCU Mode, for details. When in the external mode of operation, the external MCU or ICE is able to access the memory

mapped IO registers, the USB configuration blocks and the USB buffer space in the TAS1020B.

Texas Instruments has developed a TAS1020B evaluation module (EVM) to allow customers to develop application

firmware and to evaluate device performance. The EVM board provides a 40-pin dip socket for an ICE and headers

to allow expansion of the system in a variety of ways.

2.2.10 Interrupt Logic

The 8052 MCU core used in the TAS1020B supports the five standard 8052 MCU interrupt sources. These five

standard MCU interrupt sources are timer 0, timer 1, serial port, external 1 (INT1), and external 0 (INT0).The timer

0, timer 1, and serial port interrupts are MCU-internal interrupts, but INT0 and INT1 are external to the MCU core.

Figure 2–2 shows the associated interrupt circuitry external to the MCU core, but within the TAS1020B chip. INT0

is input into the MCU core via port 3 bit P3.2, and INT1 is input into the MCU core via port 3 bit P3.3. P3.3 can also

be configured, under firmware control, to serve as a general-purpose IO (GPIO) port bit. But the input side of P3.2

must be dedicated to servicing the INT0 function, as all additional interrupt sources from within the TAS1020B device

are ORed together to generate the INT0 signal into port 3, bit P3.2. The other interrupt sources are: the eight USB

IN endpoints, the eight USB OUT endpoints, USB function reset, USB function suspend, USB function resume, USB

start-of-frame, USB pseudo start-of-frame, USB setup stage transaction, USB setup stage transaction over-write,

codec port interface transmit data register empty, codec port interface receive data register full, I2C interface transmit

data register empty, I2C interface receive data register full, DMA channel 0, DMA channel 1, and the external interrupt

XINT.

TAS1020B датащи(PDF) 38 Page - Texas Instruments

TAS1020B датащи(HTML) 38 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL