SN74ACT3638

512

× 32 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS228D – JUNE 1992 – REVISED APRIL 1998

18

POST OFFICE BOX 655303

th(EN)

tsu(EN)

tsu(EN)

CLKA

IRB

A0 – A31

MBA

ENA

CSA

W/RA

ORA

CLKB

CSB

W/RB

MBB

ENB

B0 – B31

th(EN)

tc

th(EN)

tsu(EN)

tpd(C-IR)

FIFO2 Full

tc

tsk1†

ta

Previous Word in FIFO2 Output Register

Next Word From FIFO2

To FIFO2

Low

Low

Low

th(D)

tsu(D)

Low

Low

High

tpd(C-IR)

12

RDYB

tpd(C-R)

tpd(C-R)

tw(CLKL)

tw(CLKH)

tw(CLKL)

tw(CLKH)

† tsk1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition high in the next CLKB cycle. If the time

between the rising CLKA edge and rising CLKB edge is less than tsk1, then IRB may transition high one CLKB cycle later than shown.

Figure 10. IRB-Flag Timing and First Available Write When FIFO2 Is Full