SN74ACT3638

512

× 32 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS228D – JUNE 1992 – REVISED APRIL 1998

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POST OFFICE BOX 655303

W/RB, and ENB and with MBB high. The mail2 register flag (MBF2) is set high by a low-to-high transition on

CLKA when a port-A read is selected by CSA, W/RA, and ENA and with MBA high. The data in a mail register

remains intact after it is read and changes only when new data is written to the register.

CLKA

CLKB

RST1

0,1

th(FS)

tsu(FS)

th(RS)

tsu(RS)

FS1, FS0

IRA

tpd(C-IR)

tpd(C-IR)

ORB

tpd(C-OR)

tpd(R-F)

tpd(R-F)

AEB

AFA

MBF1

tpd(R-F)

† FIFO2 is reset in the same manner to load X2 and Y2 with a preset value.

AEA Offset

(X2)

CLKA

RST1,

RST2

FS1, FS0

0,0

CLKB

IRB

tpd(C-IR)

4

ENA

IRA

A0 – 31

th(D)

tsu(D)

tsu(EN)

th(EN)

tsk1‡

tsu(FS)

th(FS)

tpd(C-IR)

AFA Offset

(Y1)

AEB Offset

(X1)

AFB Offset

(Y2)

First Word to FIFO1

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‡ tsk1 is the minimum time between the rising CLKA edge and a rising CLKB edge for IRB to transition high in the next cycle. If the time between

the rising edge of CLKA and rising edge of CLKB is less than tsk1, then IRB may transition high one cycle later than shown.

NOTE A: CSA = L, W/RA = H, MBA = L. It is not necessary to program offset register on consecutive clock cycles.

Figure 2. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values After Reset