SN74ACT3638

512

× 32 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS228D – JUNE 1992 – REVISED APRIL 1998

9

POST OFFICE BOX 655303

synchronized FIFO flags (continued)

Table 4. FIFO1 Flag Operation

NUMBER OF WORDS

IN FIFO1†‡

SYNCHRONIZED

TO CLKB

SYNCHRONIZED

TO CLKA

IN FIFO1†‡

ORB

AEB

AFA

IRA

0

L

L

H

H

1 to X1

H

LH

H

(X1 + 1) to [512 – (Y1 + 1)]

H

HH

H

(512 – Y1) to 511

H

HL

H

512

H

H

L

L

† X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the almost-full

offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a reset of

FIFO1 or programmed from port A.

‡ When a word loaded to an empty FIFO is shifted to the output register, its

previous FIFO memory location is free.

Table 5. FIFO2 Flag Operation

NUMBER OF WORDS

IN FIFO2‡§

SYNCHRONIZED

TO CLKA

SYNCHRONIZED

TO CLKB

IN FIFO2‡§

ORA

AEA

AFB

IRB

0

L

L

H

H

1 to X2

H

LH

H

(X2 + 1) to [512 – (Y2 +1)]

H

HH

H

(512 – Y2) to 511

H

HL

H

512

H

H

L

L

‡ When a word loaded to an empty FIFO is shifted to the output register, its

previous FIFO memory location is free.

§ X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full

offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a reset

of FIFO2 or programmed from port A.

output-ready flags (ORA, ORB)

The output-ready flag of a FIFO is synchronized to the port clock that reads data from its array. When the

output-ready flag is high, new data is present in the FIFO output register. When the output-ready flag is low, the

previous data word is present in the FIFO output register and attempted FIFO reads are ignored.

A FIFO read pointer is incremented each time a new word is clocked to its output register. From the time a word

is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of the output-ready

flag synchronizing clock; therefore, an output-ready flag is low if a word in memory is the next data to be sent

to the FIFO output register and three cycles of the port clock that reads data from the FIFO have not elapsed

since the time the word was written. The output-ready flag of the FIFO remains low until the third low-to-high

transition of the synchronizing clock occurs, simultaneously forcing the output-ready flag high and shifting the

word to the FIFO output register.

A low-to-high transition on an output-ready flag synchronizing clock begins the first synchronization cycle of a

can be the first synchronization cycle (see Figures 7 and 8).