SN54ALS165, SN74ALS165

PARALLEL-LOAD 8-BIT REGISTERS

SDAS157B – JUNE 1982 – REVISED DECEMBER 1994

5

POST OFFICE BOX 655303

switching characteristics (see Figures 1, 2, and 3)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 4.5 V to 5.5 V,

CL = 50 pF,

TA = MIN to MAX†

UNIT

(INPUT)

(OUTPUT)

SN54ALS165

SN74ALS165

MIN

MAX

MIN

MAX

fmax

35

45

MHz

tPLH

SH/LD

Any

4

23

4

20

ns

tPHL

SH/LD

Any

4

23

4

22

ns

tPLH

CLK

Any

3

14

3

13

ns

tPHL

CLK

Any

3

15

3

14

ns

tPLH

H

QH

3

14

3

13

ns

tPHL

H

QH

3

18

3

16

ns

tPLH

H

QH

2

17

2

15

ns

tPHL

H

QH

3

17

3

16

ns

† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

PARAMETER MEASUREMENT INFORMATION

tw(load)

tw(load)

(disable while

clock is high)

3.5 V

0.3 V

3.5 V

0.3 V

3.5 V

0.3 V

3.5 V

0.3 V

VOH

VOL

VOH

VOL

Vref

tsu1

tw(CLK)

tw(CLK)

tsu2

tsu2

Vref

tPHL

tPLH

tPHL

tPLH

tPHL

tPLH

Vref

Vref

tPLH

tPHL

tPLH

tPHL

tPLH

tPHL

Vref

CLK INH

CLK

F and H

Inputs

(see Notes

A and B)

SH/LD

Output

QH

Output

QH

Vref

Vref

Vref

Vref

Vref

Vref

Vref

Vref

Vref

Vref

Vref

Vref

Vref

Vref

Vref

Vref

Vref

Vref

NOTES: A. The remaining six data inputs and SER are low.

B. Prior to test, high-level data is loaded into the H input.

C. The input pulse generators have the following characteristics: PRR

≤ 1 MHz, duty cycle ≤ 50%, tr = tf = 2 ns.

D. Vref = 1.3 V

Figure 1. Voltage Waveforms