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Configuration Devices for SRAM-based LUT Devices Data Sheet

IEEE Std.

1149.1 (JTAG)

Boundary-Scan

Testing

The EPC2 provides JTAG BST circuitry that complies with the IEEE Std.

1149.1-1990 specification. JTAG boundary-scan testing can be performed

before or after configuration, but not during configuration. The EPC2

device supports the JTAG instructions shown in Table 10.

The ISP circuitry in EPC2, EPC4, EPC8, and EPC16 devices is compatible

with tools that support the IEEE Std. 1532. The IEEE Std. 1532 is a standard

developed to allow concurrent ISP between multiple PLD vendors.

f For EPC4, EPC8, and EPC16 JTAG instruction, refer to the Enhanced

Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet.

f For more information, see Application Note 39 (IEEE 1149.1 (JTAG)

Boundary-Scan Testing in Altera Devices).

Figure 10 shows the timing requirements for the JTAG signals.

Table 10. EPC2 JTAG Instructions

JTAG Instruction

Description

SAMPLE/PRELOAD

Allows a snapshot of a signal at the device pins to be captured and examined during

normal device operation, and permits an initial data pattern output at the device pins.

EXTEST

Allows the external circuitry and board-level interconnections to be tested by forcing a

test pattern at the output pins and capturing results at the input pins.

BYPASS

Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST

data to pass synchronously through a selected device to adjacent devices during

normal device operation.

IDCODE

Selects the device IDCODE register and places it between TDI and TDO, allowing the

device IDCODE to be serially shifted out of TDO. The device IDCODE for the EPC2

configuration device is shown below:

0000 0001000000000010 00001101110 1

USERCODE

Selects the USERCODE register and places it between TDI and TDO, allowing the

USERCODE to be serially shifted out of TDO. The 32-bit USERCODE is a

programmable user-defined pattern.

ISP Instructions

These instructions are used when programming an EPC2 device via JTAG ports with

a MasterBlaster, ByteBlaster MV, ByteBlaster, or BitBlaster download cable, or using

a Jam STAPL File (.jam), Jam STAPL Byte-Code File (.jbc), or SVF File via an

embedded processor.

INIT_CONF

This function allows the user to initiate the APEX or FLEX configuration process by

tying nINIT_CONF to the APEX or FLEX device(s) nCONFIG pin(s). After this

instruction is updated, the nINIT_CONF pin is driven low. When the Initiate

Configuration instruction is cleared, nINIT_CONF is released, which starts the APEX

or FLEX device configuration. This instruction is used by the MAX+PLUS II software,

Jam STAPL Files, and JBC Files.

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