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Altera Corporation

Configuration Devices for SRAM-based LUT Devices Data Sheet

Table 7 describes the pin functions of all configuration devices during

FLEX 8000 device configuration.

Notes: to

Table 7

(1)

This package is available for EPC1, EPC1441, EPC1213, EPC1064, and EPC1064V devices only.

(2)

This package is available for EPC1441, EPC1064, and EPC1064V devices only.

(3)

The EPC1441, EPC1064, and EPC1064V devices do not support data cascading. The EPC1 and EPC1213 devices

support data cascading for FLEX 8000 devices.

following documents:

■

Application Note 33 (Configuring FLEX 8000 Devices)

■

Application Note 38 (Configuring Multiple FLEX 8000 Devices)

Table 7. Configuration Device Pin Functions During FLEX 8000 Device Configuration

Pin Name

Pin Number

Pin

Type

Description

8-Pin

PDIP (1)

20-Pin

PLCC

32-Pin

TQFP (2)

DATA

12

31

Output

Serial data output. The DATA pin is tri-stated before

configuration when the nCS pin is high and after the

configuration device finishes sending its configuration

data. This operation is independent of the device’s

position in the cascade chain.

DCLK

24

2

Input

DCLK

is a clock input when using EPC1, EPC1213,

EPC1064, and EPC1064V configuration devices. Rising

edges on DCLK increment the internal address counter

and present the next bit of data to the DATA pin. The

counter is incremented only if the OE input is held high,

the nCS input is held low, and all configuration data has

not been transferred to the target device.

OE

38

7

Open-

Drain

I/O

Output enable (active high) and reset (active low). A low

logic level resets the address counter. A high logic level

enables DATA and permits the address counter to count.

nCS

(3)

4

9

10

Input

Chip-select input (active low). A low input allows DCLK to

increment the address counter and enables DATA.

nCASC

6

12

15

Output

Cascade-select output (active low). This output goes low

when the address counter has reached its maximum

value. The nCASC output is usually connected to the nCS

input of the next device in a configuration chain, so the

next DCLK clocks data out of the next device.

VCC

7, 8

20

27

Power

Power pin.

GND

5

10

12

Ground Ground pin. A 0.2-

µF decoupling capacitor must be

placed between the VCC and GND pins.