| поискавой системы для электроныых деталей |
|
LTC4098-1 датащи(PDF) 24 Page - Linear Technology |
|
|
|||||||||||||||||||||||||||||
LTC4098-1 датащи(HTML) 24 Page - Linear Technology |
|
24 / 32 page ![]() LTC4098/LTC4098-1 24 40981fb exceeds 6V plus VF(SCHOTTKY), OVGATE will be pulled to GND and both the WALL and USB inputs will be protected. Each input is protected up to the drain-source breakdown, BVDSS, of MN1 and MN2. R1 must also be rated for the power dissipated during maximum overvoltage. See the Operations section for an explanation of this calculation. Table 4 shows some N-channel MOSFETs that may be suitable for overvoltage protection. Alternate NTC Thermistors and Biasing The LTC4098/LTC4098-1 provide temperature-qualified charging if a grounded thermistor and a bias resistor are connected to NTC and NTCBIAS. By using a bias resistor whose value is equal to the room temperature resistance of the thermistor (R25) the upper and lower temperatures are preprogrammed to approximately 40°C and 0°C, re- spectively (assuming a Vishay curve 1 thermistor). The upper and lower temperature thresholds can be ad- justed by either a modification of the bias resistor value or by adding a second adjustment resistor to the circuit. If only the bias resistor is adjusted, then either the upper or the lower threshold can be modified but not both. The other trip point will be determined by the characteristics of the thermistor. Using the bias resistor in addition to an R2 R1 USB/WALL ADAPTER 40981 F08 C1 D1 MN1 MP1 VBUS POSITIVE PROTECTION UP TO BVDSS OF MN1 VBUS NEGATIVE PROTECTION UP TO BVDSS OF MP1 VBUS OVSENS OVGATE LTC4098/ LTC4098-1 Figure 8. Dual-Polarity Voltage Protection Table 4. Recommended OVP FETs N-CHANNEL MOSFET BVDSS RON PACKAGE Si2302ADS 20V 70m Ω SOT-23 IRLML2502 20V 35m Ω SOT-23 Si1472DH 30V 65m Ω SC70-6 NTLJS4114N 30V 20m Ω 2mm × 2mm DFN FDN372S 30V 45m Ω SOT-23 Reverse Voltage Protection The LTC4098/LTC4098-1 can also be easily protected against the application of reverse voltage, as shown in Figure 8. D1 and R1 are necessary to limit the maximum VGS seen by MP1 during positive overvoltage events. D1’s breakdown voltage must be safely below MP1’s BVGS. The circuit shown in Figure 8 offers forward volt- age protection up to MN1’s BVDSS and reverse voltage protection up to MP1’s BVDSS. APPLICATIONS INFORMATION |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |