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LTC2921IGN датащи(PDF) 14 Page - Linear Technology |
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LTC2921IGN датащи(HTML) 14 Page - Linear Technology |
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14 / 20 page ![]() LTC2921/LTC2922 Series 14 29212fa APPLICATIO S I FOR ATIO pin has fully ramped up. The switches are N-channel MOSFETs whose gates are ramped from ground to VPUMP at a nominal rate of 8V/ms. The PG pin is activated upon completion of the TIMER delay cycle that follows GATE ramp-up and remote sense switch activation. When con- ditions indicate a supply disconnect, the switches shut off in less than 10 µs. Figure 10 shows an example of how to connect a switch to remote sense the load voltage. Although only one remote sense switch is referred to in this section, the calculations and comments apply to all. Before the activation of Q1 and the internal switch, resistor RX1 provides a direct path between the DC/DC converter’s output voltage and its feedback network (RY1 and RZ1). Once Q1 activates, the supply energizes the load. When the internal switch turns on, it provides a remote sense path between the load voltage and the converter’s feed- back network. To choose a value for resistor RX1, consider the remote sense switch connection equivalent network in Figure 11. Resistor RQ1(ON) represents the on-resistance of Q1, and resistor RFB1(ON) represents the on-resistance of the inter- nal switch. To allow the load voltage to dominate the feedback to the converter when the internal switch is closed, make RX1 >> RFB1(ON). To set the converter feedback ratio accurately with RY1 and RZ1, make both RX1 and RFB1(ON) much less than (RY1 + RZ1). To ensure that most of the load current flows through the external N-channel FET, choose (RX1 + RFB1(ON)) >> RQ1(ON). Summarized, these requirements amount to: RQ1(ON), RFB(ON) << RX1 << (RY1 + RZ1) (11) Approach the selection of RX1 in the following way: design the DC/DC converter feedback based on the resistive divider formed by RY1 and RZ1 with VS1 at the desired supply voltage value. When the resistor values satisfy Equation 11, Equations 12 through 15 are valid. PG ENABLE 4 µA PG VCC SENSE RSENSE GATE VL0 VSRC0 GND CGATE RG0 10 Ω RPG 2921/22 F08 Q0 LTC2922 µC RESET VPUMP PG ENABLE 4 µA PG VCC SENSE RSENSE GATE VL0 VL5 VSRC0 VSRC5 GND CGATE CPG RG0 10 Ω RG5 10 Ω 2921/22 F09 Q0 Q5 LTC2922 VPUMP 2921/22 F10 RX1 RY1 RZ1 VSRC1 VOUT VFB GND DC/DC CONVERTER LTC2922 V1 GND GATE Q1 CGATE LOAD RB1 RG1 10 Ω RA1 VL1 S1 D1 VS1 2921/22 F11 LTC2922 S1 D1 LOAD IDS1 IQ1 RX1 RFB1(ON) RQ1(ON) RY1 RZ1 VSRC1 VL1 VS1 IL1 VOUT VFB GND DC/DC CONVERTER Figure 9. PG Pin as Sequenced N-Channel Gate Driver Figure 8. PG Pin as Logic Output Figure 10. Automatic Remote Sense Switching Connection Figure 11. Remote Sense Switch Connection Equivalent Network |
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