LTC2921IGN datasheet(12/20 Pages) LINER

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LTC2921/LTC2922 Series

29212fa

voltage specifications. On-resistance is a critical param-

eter when choosing power MOSFETs. The integrated

remote sense switches compensate for IR drops, but

minimizing VQ(MAX) leaves more margin for designing the

resistive voltage divider for the monitors.

Setting the GATE Ramp Rate

Application of power to the loads is controlled by setting

the voltage ramping rate with an external capacitor on the

GATE pin. During Step 3 of the monitoring sequence, a

µA pull-up ramps the GATE pin capacitance up to

VPUMP, the internal charge pump voltage. Use Equation 5

to calculate the nominal GATE pin capacitance necessary

to achieve a given ramp rate,

∆V/∆t:

GATE =

∆∆

(5)

Alternatively, to calculate the GATE capacitor to achieve a

desired nominal ramp time, use Equation 6. The GATE

drive voltage (VGATE) varies with VCC voltage. Consult the

Electrical Characteristics table and Typical Performance

curves to choose an appropriate value to insert for VGATE.

GATE

RAMP

GATE

= µ

•

(6)

When the GATE pin drives several FETs in parallel, the load

voltages ramp together at the same rate until the lowest

supply reaches its full value. The other supplies continue

to track until the next lowest supply reaches its full value,

and so on.

The GATE pin must not be forced above the level it reaches

when fully ramped. An internal clamp limits the GATE

voltage to

≤12.2V relative to ground.

Damp possible ramp-on oscillations by including a 10

Ω

resistor in series with each external N-channel gate, and as

necessary, a 0.1

µF capacitor on each external N-channel

drain, as shown in Figure 6.

Setting the Sequence Delay Timer

The turn-on sequence includes two programmable delays

set by the capacitance on the TIMER pin. More precisely,

a single delay value is used at two points in the sequence.

APPLICATIO S I FOR ATIO

In both cases, the delay provides a measure of confidence

that conditions are stable enough for the sequence to

advance.

The first TIMER delay begins once all monitor voltages

comply with their thresholds, the electronic circuit breaker

has not tripped, and VCC is not undervoltage. The TIMER

pin sources 2

µA into an external capacitor, which ramps

its voltage. A comparator trips when the TIMER pin voltage

reaches the internal 1.2V reference, then the GATE ramp

begins, and TIMER is pulled to ground. The second TIMER

delay begins after the gate of the remote sense switches is

fully ramped up. After the TIMER ramp completes, the PG

pin is activated. An internal circuit pulls-down the TIMER

pin with >100

µA of current at all times, except during the

ramping periods, and when VCC is undervoltage.

Calculate the nominal value for the timing capacitor by

inserting the desired delay into Equation 7:

TIMER

DLY

= µ

•

(7)

For delay times below 60

µs, be sure to limit stray capaci-

tances on the TIMER pin by using good PCB design

practices. To program essentially no delay (<1

µs), float

the TIMER pin.

Internal circuitry guarantees that the TIMER pin is pulled

below 150mV (typical) before a delay cycle can begin.

LTC2922

GND

GATE

RG2

Ω

RG1

Ω

RG0

Ω

CGATE

CD2

0.1

µF

(OPT)

CD1

0.1

µF

(OPT)

CD0

0.1

µF

(OPT)

VSRC2

VSRC1

VSRC0

2921/22 F06

VL2

VL1

VL0

Figure 6. Ramping and Damping Components on GATE Pin

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