GRSPW datasheet(21/48 Pages) ACTEL

21 / 48 page

GRSPW / GRSPW-FT

December 2008, Version 1.0.2

GAISLER

2.7

AMBA interface

The AMBA interface consists of an APB interface, an AHB master interface and DMA FIFOs. The

APB interface provides access to the user registers which are described in section 2.9. The DMA

engines have 32-bit wide FIFOs to the AHB master interface which are used when reading and writ-

ing to the bus.

The transmitter DMA engine reads data from the bus in bursts which are half the FIFO size in length.

A burst is always started when the FIFO is half-empty or if it can hold the last data for the packet. The

burst containing the last data might have shorter length if the packet is not an even number of bursts in

size.

The receiver DMA works in the same way except that it checks if the FIFO is half-full and then per-

forms a burst write to the bus which is half the fifo size in length. The last burst might be shorter. If

the rmap or rxunaligned VHDL generics are set to 1 the interface also handles byte accesses. Byte

accesses are used for non word-aligned buffers and/or packet lengths that are not a multiple of four

bytes. There might be 1 to 3 single byte writes when writing the beginning and end of the received

packets.

2.7.1

APB slave interface

As mentioned above, the APB interface provides access to the user registers which are 32-bits in

width. The accesses to this interface are required to be aligned word accesses. The result is undefined

if this restriction is violated.

2.7.2

AHB master interface

The core contains a single master interface which is used by both the transmitter and receiver DMA

engines. The arbitration algorithm between the channels is done so that if the current owner requests

the interface again it will always acquire it. This will not lead to starvation problems since the DMA

engines always deassert their requests between accesses.

if rmap and rxunaligned are disabledThe AHB accesses can be of size byte, halfword and word

(HSIZE = 0x000, 0x001, 0x010) otherwise. Byte and halfword accesses are always NONSEQ.

The burst length will be half the AHB FIFO size except for the last transfer for a packet which might

be smaller. Shorter accesses are also done during descriptor reads and status writes.

The AHB master also supports non-incrementing accesses where the address will be constant for sev-

eral consecutive accesses. HTRANS will always be NONSEQ in this case while for incrementing

accesses it is set to SEQ after the first access. This feature is included to support non-incrementing

reads and writes for RMAP.

If the core does not need the bus after a burst has finished there will be one wasted cycle (HTRANS =

IDLE).

BUSY transfer types are never requested and the core provides full support for ERROR, RETRY and

SPLIT responses.

2.8

Synthesis and hardware

2.8.1

Clock-generation

Figure 8 shows the clock recovery scheme for the receiver. Data and strobe are coupled directly from

their pads to an xor gate which generates the clock. The output from the xor is then connected to a

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