GRSPW datasheet(13/48 Pages) ACTEL

13 / 48 page

GRSPW / GRSPW-FT

December 2008, Version 1.0.2

GAISLER

2.5.1

Basic functionality

The transmit DMA engine reads data from the AHB bus and stores them in the transmitter FIFO for

transmission on the SpaceWire network. Transmission is based on the same type of descriptors as for

the receiver and the descriptor table has the same alignment and size restrictions. When there are new

descriptors enabled the core reads them and transfer the amount data indicated.

2.5.2

Setting up the core for transmission

Four steps need to be performed before transmissions can be done with the core. First the link inter-

face must be enabled and started by writing the appropriate value to the ctrl register. Then the address

to the descriptor table needs to be written to the transmitter descriptor table address register and one or

more descriptors must also be enabled in the table. Finally, the txen bit in the DMA control register

should be written with a one which triggers the transmission. These steps will be covered in more

detail in the next sections.

2.5.3

Enabling descriptors

The descriptor table address register works in the same way as the receiver’s corresponding register

which was covered in section 2.4.

To transmit packets one or more descriptors have to be initialized in memory which is done in the fol-

lowing way: The number of bytes to be transmitted and a pointer to the data has to be set. There are

two different length and address fields in the transmit descriptors because there are separate pointers

for header and data. If a length field is zero the corresponding part of a packet is skipped and if both

are zero no packet is sent. The maximum header length is 255 bytes and the maximum data length is

16 Mbyte - 1. When the pointer and length fields have been set the enable bit should be set to enable

the descriptor. This must always be done last. The other control bits must also be set before enabling

the descriptor.

The transmit descriptors are 16 bytes in size so the maximum number in a single table is 64. The dif-

ferent fields of the descriptor together with the memory offsets are shown in the tables below.

The HC bit should be set if RMAP CRC should be calculated and inserted for the header field and

correspondingly the DC bit should be set for the data field. This field is only used by the core when

the CRC logic is available (rmap or rmapcrc VHDL generic set to 1). The header CRC will be calcu-

lated from the data fetched from the header pointer and the data CRC is generated from data fetched

from the data pointer. The CRCs are appended after the corresponding fields. The NON-CRC bytes

field is set to the number of bytes in the beginning of the header field that should not be included in

the CRC calculation. The CRCs are sent even if the corresponding length is zero.

When both header and data length are zero no packet is sent not even an EOP.

2.5.4

Starting transmissions

When the descriptors have been initialized, the transmit enable bit in the DMA control register has to

be set to tell the core to start transmitting. New descriptors can be activated in the table on the fly

(while transmission is active). Each time a set of descriptors is added the transmit enable register bit

should be set. This has to be done because each time the core encounters a disabled descriptor this

Table 4. GRSPW transmit descriptor word 0 (address offset 0x0)

18 17 16 15 14 13 12 11

RESERVED

DC HC LE IE WR EN

NONCRCLEN

HEADERLEN

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