Advance Data Sheet #: SG036

Page 3 of 16

Rev: A02

Date: 10/25/01

NOTES:

1.0

Operation of the device at these or any other condition beyond those listed under Operating Specifications is not implied.

Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.

2.0

Requires external regulation and supply decoupling. (22 uF, 330 pF)

3.0

3db loop response.

4.0

From a 20 PPM step in reference frequency at 25°C @ 3.3V

5.0

50-ohm load biased to 1.3 volts.

6.0

Jitter based on SONET OC-48 bandwidth. (12KHz to 20 MHz)

7.0

Entry into Free Run doesn’t meet requirement for initial 2.33 seconds of self-timing.

7.1

If the selected reference is removed system response to the ALARM must be less than 10µs.

Absolute Maximum Rating

Table 1

Symbol

Parameter

Minimum

Nominal

Maximum

Units

Notes

V

cc

Power Supply Voltage

-0.5

-

+4.0

Volts

1.0

V

i

Input Voltage

-0.5

-

+5.5

Volts

1.0

T

s

Storage Temperature

-65.0

-

+100

°C

1.0

Operating Specifications

Table 2

Symbol

Parameter

Minimum

Nominal

Maximum

Units

Notes

V

cc

Power Supply Voltage

3.135

3.3

3.465

Volts

2.0

I

cc

Power Supply Current

170

250

320

mA

5.0

T

o

Temperature Range

0

-

70

°C

F

REF

External Reference Frequency

19.44

MHz

F

fr

Free Run Frequency

-20

-

20

ppm

F

LV

LVPECL Differential Output Frequency

155.52

MHz

F

CM

CMOS Output Frequency

51.84

MHz

F

cap

Capture/pull-in range

-25

-

25

ppm

F

bw

Jitter Filter Bandwidth

-

-

10

Hz

3.0

T

jtol

Input Jitter Tolerance

-

-

6.25

µs

T

aq

Acquisition Time

-

1

-

s

4.0

T

rf

Output Rise and Fall Time (20% 80%)

100

225

350

ps

5.0

LV

DC

LVPECL Output Duty Cycle

40

60

%

CM

DC

CMOS Output Duty Cycle

40

60

%

LV

S

LVPECL Output Jitter (OC-48)

<1

psRMS

6.0

CM

S

CMOS Output Jitter

3

5

psRMS

6.0

MTIE

sr

MTIE at Synchronization Rearrangement

GR-253-CORE.1999 R5-136

7.0, 7.1