SCG4521 datasheet(2/16 Pages) CONNOR-WINFIELD

2 / 16 page

Advance Data Sheet #: SG036

Page 2 of 16

Rev: A02

Date: 10/25/01

8 KHz PHASE

ALIGNER

REFB

REFA

SELAB

DPFD

ANALOG

FILTER

1 / N

ALARM

LOW JITTER

155.52 MHz

VCXO

CMOS

Output

General Description

The SCG4521 is a mixed-signal phase locked loop

generating LVPECL outputs from an intrinsically low

jitter, voltage controlled, crystal oscillator. The LVPECL

outputs may be disabled.

The SCG4521 can lock to one of two external

references, which is selectable using the SEL

AB input

select pin. The unit has a fast acquisition time of about

1.5 seconds and it is tolerant of different reference duty

cycles.

The SCG4521 provides two types of output logic.

The primary output is a differential LVPECL output at

155.52 MHz. The secondary output is a CMOS output

at 51.84 MHz that is derived from the LVPECL output.

Both outputs are phase aligned to the selected input

reference.

The SCG4521 includes an alarm output that

indicates deviations from normal operation. If a Loss-

of-Reference (LOR) or Loss-of-Lock (LOL) is detected

the alarm with indicate the need for a reference

rearrangement. If both references A and B are absent

the module will enter Free Run operation. The FR

status

pin will indicate that the module is in Free Run

operation. Frequency stability during Free Run

operation is guaranteed to ±20 ppm. Additionally the

Free Run mode may be entered manually.

The package dimensions are 1” x 1” x .45” on a 6

layer FR4 board with castellated pins. Parts are

assembled using high temperature solder to withstand

63/37 alloys, 180°C surface mount reflow processes.

Package Outline

Figure 1

Block Diagram

Figure 2

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