5

Rev. D

04/17/02

HV302 / HV312

In Feedback Capacitor Mode operation, assuming the UV and

OV limits are satisfied and while continuing to hold the PWRGD

flags inactive and the external MOSFET GATE voltage low, the

current source feeding the RAMP pin is turned on. The external

delay determined by the equivalent value of the capacitors and the

2Vbg threshold voltage of the RAMP pin. During this time if the

OV or UV limits are exceeded, an immediate reset occurs, the

ramp capacitor is discharged and the feedback capacitor is

recharged.

When the voltage on the RAMP pin exceeds the 2Vbg threshold

voltage, the gate drive circuit begins to apply voltage to the gate of

the external MOSFET, which begins to turn on when its gate

threshold voltage is reached. However, the source current from

load capacitor. At this point essentially all available current from

the RAMP pin flows into the feedback capacitor, thus the voltage

on the ramp capacitor and the RAMP pin remains essentially

constant, thereby limiting and controlling the gate voltage of the

external MOSFET (See Programming Current Limit and Circuit

Breaker in Design Information section). When the load capacitor is

fully charged the current flowing into the feedback capacitor is

reduced and the voltage drop across the MOSFET essentially

drops to zero, effectively connecting the feedback capacitor in

parallel with the ramp capacitor. Now the current from the RAMP

pin flows into the parallel-connected capacitors and the voltage on

the RAMP pin begins to rise, thereby providing yet another

programmed delay.

Whether operating in Servo Mode or Feedback Capacitor Mode,

when the ramp voltage is within 1.2V of the regulated internal

supply voltage, the controller will force the GATE terminal to a

nominal 10V, the PWRGD-A pin will change to an active state and

the Circuit Breaker is enabled. PWRGD-B will change to an active

state a programmed delay time after PWRGD-A went active,

PWRGD-C will change to an active state a programmed delay time

after PWRGD-B went active, PWRGD-D will change to an active

state a programmed delay time after PWRGD-C went active and

the circuit transitions to a low power sleep mode. While in sleep

mode the circuit continues to monitor the current and the OV and

UV status.

When the voltage on the SENSE pin rises to 100mV, indicating an

over current condition, the circuit breaker will trip in less than 5

µs.

This time may be extended by the addition of external

components.

If due to output overload conditions during startup full charging of

the load is not achieved within 100ms or a load fault occurs at any

time the circuit breaker is tripped, the MOSFET is turned off by

Thereafter an auto-retry timer, programmed by the capacitor

connected to the RAMP pin, will hold the pass device off to allow it

to cool before resetting and restarting. The auto-retry can be

disabled using a single resistor if desired (See Auto-Retry and

Auto-Retry Disable in Design Information section).

At any time during the start up cycle or thereafter, crossing the UV

and OV limits (including hysteresis) will cause an immediate reset

of all internal circuitry. When the input supply voltage returns to a

value within the programmed UV and OV limits a new start up

sequence will be immediately initiated.

Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 Fax: (408) 222-4895 www.supertex.com