9

Rev. D

04/17/02

HV302 / HV312

Start up Overload Protection

Start up must be achieved within a nominal 100ms as indicated by

the PWRGD-A pin transition to the active state or the circuit will

reset and an Auto-Retry will initiate. If there is an output overload

or short circuit during start up, the circuit will be in current limit

mode for the 100ms time limit (in servo mode).

In feedback

capacitor mode the circuit breaker will shutdown the MOSFET

before 100ms.

Circuit Breaker Delay

The circuit breaker will trip in less than 5

µs when the voltage on

the SENSE pin reaches a nominal 100mV. A resistor in series with

the SENSE pin and a capacitor connected between the SENSE

and VEE pins may be added to delay the rate of voltage rise on the

SENSE pin, thus permitting a current overshoot and delaying

Circuit Breaker activation. This method is particularly useful when

operating in Feedback Capacitor Mode. However, in Servo Mode

operation it will result in a current limit leading edge overshoot.

Auto-Retry and Auto-Retry Disable

The Auto-Retry delay time is directly proportional to the

capacitance at the RAMP pin. Auto-Retry sequence is activated

whenever the 100ms timeout is reached during start up or the

Circuit Breaker is tripped.

Auto-Retry can be approximated as a 555-timer with 2.5

µA charge

up and charge down currents through 8V, to a count of 256.

Therefore,

RAMP

try

Re

Auto

C

A

5

.

2

256

8

2

t

×

µ

×

×

=

−

s

4

.

16

nF

10

A

5

.

2

256

8

2

t

try

Re

Auto

=

×

µ

×

×

=

−

Due to the 2.5

µA maximum charge current a resistor which draws

more than 2.5

µA below 8V will disable Auto-Retry. Try to keep this

resistor as big as possible, e.g. 2.5M

Ω. For most MOSFETs with

maximum Vt of 4V, this will vary the 10

µA RAMP current source by

only

A

6

.

1

M

5

.

2

V

4

µ

=

Ω

PWRGD Flag Delay Programming

Shortly after current limiting ends, PWRGD-A becomes active

indicating successful completion of the Hotswap operation.

PWRGD-B will change to an active state a programmed delay time

after PWRGD-A went active, PWRGD-C will change to an active

state a programmed delay time after PWRGD-B went active and

PWRGD-D will change to an active state a programmed delay time

after PWRGD-C went active.

Resistors connected from the

delay times between the PWRGD flags sequentially going active.

The following waveforms demonstrate the sequencing of the

= 60k

The value of the resistors determines the capacitor charging and

discharging current of a triangle wave oscillator. The oscillator

output is fed to an 8-bit counter to generate the desired time delay.

The respective delay time is defined by the following equation:

CD

PP

OSC

TX

I

V

C

2

255

t

×

×

×

=

and

TX

bg

CD

R

4

V

I

=

Where

Vbg = 1.2V (Internal Band Gap Reference)

V

2

.

8

pF

120

2040

t

V

2

.

1

V

C

2040

t

B

R

TX

PP

PP

TX

bg

TX

×

×

×

=

×

×

×

=

TX

6

TX

t

10

6

.

0

R

×

×

=

For a delay time of 200ms we get:

() (

)

Ω

=

×

×

×

=

−

k

120

10

200

10

6

.

0

R

3

6

TX

For a delay time of 5ms we get:

() (

=

×

×

×

=

−

k

3

10

5

10

6

.

0

R

3

6

TX

Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 Fax: (408) 222-4895 www.supertex.com