3

Rev. D

04/17/02

Power Good Pin Breakdown Voltage

90

V

PWRGD-x = HI Z

Power Good Pin Output Low Voltage

0.5

0.8

V

Maximum Leakage Current

<1.0

10

µA

Dynamic Characteristics

OV Comparator Transition

500

ns

UV Comparator Transition

500

ns

Note 1:

This timing depends on the threshold voltage of the external N-Channel MOSFET. The higher its threshold is, the longer this timing.

Note 2:

*IRF530 is a registered trademark of International Rectifier.

Pinout

4

5

6

7

8

9

10

11

1

2

3

12

13

14

PWRGD-D (HV312)

________

PWRGD-D (HV302)

PWRGD-C (HV312)

________

PWRGD-C (HV302)

PWRGD-B (HV312)

________

PWRGD-B (HV302)

PWRGD-A (HV312)

________

PWRGD-A (HV302)

OV

UV

VEE

VDD

TD

TC

TB

RAMP

GATE

SENSE

PWRGD Logic

Model

Condition

PWRGD-A/B/C/D

INACTIVE (Not Ready)

0

HV302

ACTIVE (Ready)

1

HI Z

INACTIVE (Not Ready)

1

HI Z

HV312

ACTIVE (Ready)

0

Pin Description

PWRGD-D – This Power Good Output Pin is held inactive on initial

power application and goes active a programmed time delay after

PWRGD-C goes active.

PWRGD-C – This Power Good Output Pin is held inactive on initial

power application and goes active a programmed time delay after

PWRGD-B goes active.

PWRGD-B – This Power Good Output Pin is held inactive on initial

power application and goes active a programmed time delay after

PWRGD-A goes active.

PWRGD-A – This Power Good Output Pin is held inactive on initial

power application and goes active when the external MOSFET is

fully turned on.

OV – This Over Voltage (OV) sense pin, when raised above its

high threshold will immediately cause the GATE pin to be pulled

low. The GATE pin will remain low until the voltage on this pin falls

below the low threshold limit, initiating a new start-up cycle.

UV – This Under Voltage (UV) sense pin, when below its low

threshold limit will immediately cause the GATE pin to be pulled

low. The GATE pin will remain low until the voltage on this pin

rises above the high threshold limit, initiating a new start-up cycle.

the circuit.

the circuit.

delay from PWRGD-C going active to PWRGD-D going active.

delay from PWRGD-B going active to PWRGD-C going active.

delay from PWRGD-A going active to PWRGD-B going active.

RAMP – This pin provides a current output so that a timing ramp

voltage is generated when a capacitor is connected.

GATE – This is the Gate Driver Output for the external N-Channel

MOSFET.

Pin programs the servo control current limit and the circuit breaker

trip limit.

Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 Fax: (408) 222-4895 www.supertex.com